| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 02/16/2006 | WO2005078729A3 High voltage driver circuit with fast reading operation |
| 02/16/2006 | US20060034145 Synchronous semiconductor memory device of fast random cycle system and test method thereof |
| 02/16/2006 | US20060034144 Method and device for driving a display device with line-wise dynamic addressing |
| 02/16/2006 | US20060034143 Semiconductor memory device having the operating voltage of the memory cell controlled |
| 02/16/2006 | US20060034142 Non-volatile semiconductor memory device and semiconductor memory device |
| 02/16/2006 | US20060034141 Nonvolatile semiconductor memory |
| 02/16/2006 | US20060034140 Semiconductor memory device |
| 02/16/2006 | US20060034139 Semiconductor memory device |
| 02/16/2006 | US20060034133 Semiconductor memory |
| 02/16/2006 | US20060034118 Magneto-resistance effect element, magnetic memory and magnetic head |
| 02/16/2006 | DE10335978B4 Hub-Baustein zum Anschließen von einem oder mehreren Speicherbausteinen Hub module for connecting one or more storage devices |
| 02/16/2006 | DE102005035136A1 Semiconductor module e.g. static RAM module, supplies power to bitlines and complementary bitlines based on control signals generated based on setting signal and initial data value during initial data value |
| 02/15/2006 | CN1735944A Refresh control circuit for ics with a memory array |
| 02/15/2006 | CN1734665A Ferroelectric memory device and its driving method |
| 02/15/2006 | CN1242477C Semiconductor integrated circuit |
| 02/15/2006 | CN1242475C Electric-level moving device |
| 02/15/2006 | CN1242334C Embedded MRAM containing dual read port |
| 02/14/2006 | US7000139 Interface circuit for selectively latching between different sets of address and data registers based on the transitions of a frequency-divided clock |
| 02/14/2006 | US7000063 Write-many memory device and method for limiting a number of writes to the write-many memory device |
| 02/14/2006 | US6999375 Synchronous semiconductor device and method of preventing coupling between data buses |
| 02/14/2006 | US6999374 CMOS image sensor having row decoder capable of shutter timing control |
| 02/14/2006 | US6999373 High speed wordline decoder for driving a long wordline |
| 02/14/2006 | US6999372 Multi-ported memory cell |
| 02/14/2006 | US6999358 Semiconductor memory device |
| 02/14/2006 | US6999357 Memory circuit with redundant memory cell array allowing simplified shipment tests and reduced power consumptions |
| 02/14/2006 | US6999353 Semiconductor memory device including page latch circuit |
| 02/14/2006 | US6998878 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit |
| 02/09/2006 | US20060028906 Clock-synchronous semiconductor memory device |
| 02/09/2006 | US20060028905 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM |
| 02/09/2006 | US20060028904 Reduced power registered memory module and method |
| 02/09/2006 | US20060028903 Image processing device, and control method of image processing device |
| 02/09/2006 | US20060028902 Digital delay buffers and related methods |
| 02/09/2006 | US20060028901 Circuit layout with active components and high breakdown voltage |
| 02/09/2006 | US20060028900 Memory device employing open bit line architecture for providing identical data topology on repaired memory cell block and method thereof |
| 02/09/2006 | US20060028899 DRAM boosted voltage supply |
| 02/09/2006 | US20060028898 Memory bit line segment isolation |
| 02/09/2006 | US20060028897 Byte enable logic for memory |
| 02/09/2006 | US20060028894 Programmable semi-fusible link read only memory and method of margin testing same |
| 02/09/2006 | US20060028893 Semiconductor memory device, refresh control method thereof, and test method thereof |
| 02/09/2006 | US20060028884 Nonvolatile semiconductor memory device |
| 02/09/2006 | DE102005034611A1 Speichersystem und zugehörige Betriebs- und Blockverwaltungsverfahren Storage system and associated operating and block management process |
| 02/09/2006 | DE102004005667B4 Integrierter Halbleiterspeicher mit temperaturabhängiger Spannungserzeugung und Verfahren zum Betrieb Integrated semiconductor memory with temperature-dependent voltage generator and method for operating |
| 02/08/2006 | EP1624558A1 Semiconductor integrated circuit device |
| 02/08/2006 | EP1624487A2 Semiconductor device having vertically stacked field effect transistors and methods of manufacturing the same |
| 02/08/2006 | EP1623430A2 Semiconductor memory device and method of operating same |
| 02/08/2006 | EP1490875A4 Asynchronous interface circuit and method for a pseudo-static memory device |
| 02/08/2006 | CN1732537A Method of addressing individual memory devices on a memory module |
| 02/08/2006 | CN1241203C Thin film magnet storage device capable of high-speed data reading data and working stably |
| 02/08/2006 | CN1241114C Device and method for protecting data by confusion processing of bit address wire |
| 02/07/2006 | US6996685 Device for accessing registered circuit units |
| 02/07/2006 | US6996203 Bidirectional shift register and display device incorporating same |
| 02/07/2006 | US6996027 Synchronous memory device |
| 02/07/2006 | US6996026 Devices for synchronizing clock signals |
| 02/07/2006 | US6996025 Integrated circuit memory devices having zig-zag arrangements of column select IO blocks to increase input/output line routing efficiency |
| 02/07/2006 | US6996016 Echo clock on memory system having wait information |
| 02/02/2006 | US20060023564 Signal output device and method for the same |
| 02/02/2006 | US20060023563 Pseudo SRAM with common pad for address pin and data pin |
| 02/02/2006 | US20060023562 Delay stage-interweaved analog DLL/PLL |
| 02/02/2006 | US20060023561 Nonvolatile magnetic memory device and manufacturing method thereof |
| 02/02/2006 | US20060023560 Structure for directly burning program into motherboard |
| 02/02/2006 | US20060023559 Method for assaying for natural killer, cytotoxic T-lymphocyte and neutrophil-mediated killing of target cells using real-time microelectronic cell sensing technology |
| 02/02/2006 | US20060023558 Non-volatile memory devices that include a selection transistor having a recessed channel and methods of fabricating the same |
| 02/02/2006 | US20060023557 Multiport memory |
| 02/02/2006 | US20060023556 Integrated semiconductor memory with redundant memory cells |
| 02/02/2006 | US20060023555 Semiconductor memory device allowing high-speed data reading |
| 02/02/2006 | US20060023554 Nonvolatile memory apparatus |
| 02/02/2006 | US20060023553 Semiconductor device having hierarchized bit lines |
| 02/02/2006 | US20060023541 FIFO with multiple data inputs and method thereof |
| 02/02/2006 | US20060023530 Clock signal initiated precharge technique for active memory subarrays in dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded DRAM |
| 02/02/2006 | US20060023525 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface |
| 02/02/2006 | US20060023523 Integrated semiconductor memory |
| 02/02/2006 | US20060022704 Reconfigurable electronic device having interconnected data storage devices |
| 02/02/2006 | DE112004000588T5 Schneller und genauer Spannungshochsetzer mit geringer Versorgungsspannung unter Anwendung eines A/D-Wandlers Faster and more precise voltage booster with a low supply voltage using a A / D converter |
| 02/02/2006 | DE10356851B4 Schieberegister zum sicheren Bereitstellen eines Konfigurationsbits Shift register for providing a safe configuration bits |
| 02/01/2006 | CN1729541A Tamper-resistant packaging and approach |
| 02/01/2006 | CN1729540A Tamper-resistant packaging and approach |
| 02/01/2006 | CN1729539A Method and device for protection of an MRAM device against tampering |
| 02/01/2006 | CN1728278A Method of operating a semiconductor device and the semiconductor device |
| 01/31/2006 | US6993691 Series connected TC unit type ferroelectric RAM and test method thereof |
| 01/31/2006 | US6992950 Delay locked loop implementation in a synchronous dynamic random access memory |
| 01/31/2006 | US6992949 Method and circuit for controlling generation of column selection line signal |
| 01/31/2006 | US6992948 Memory device having address generating circuit using phase adjustment by sampling divided clock to generate address signal of several bits having one bit changed in sequential order |
| 01/31/2006 | US6992947 Dual-port SRAM in a programmable logic device |
| 01/31/2006 | US6992945 Fuse circuit |
| 01/31/2006 | US6992944 Semiconductor memory device with reduced power consumption for refresh operation |
| 01/31/2006 | US6992534 Circuits and methods of temperature compensation for refresh oscillator |
| 01/26/2006 | US20060020747 Moving sectors within a block of information in a flash memory mass storage architecture |
| 01/26/2006 | US20060018185 Memory control apparatus and electronic apparatus |
| 01/26/2006 | US20060018184 Source controlled operation of non-volatile memories |
| 01/26/2006 | US20060018183 Content addressable memory cell |
| 01/26/2006 | US20060018182 Solid state microoptoelectromechanical system (moens) for reading photonics diffractive memory |
| 01/26/2006 | US20060018181 Nonvolatile semiconductor memory |
| 01/26/2006 | US20060018180 Nonvolatile semiconductor memory with x8/x16 operation mode using address control |
| 01/26/2006 | US20060018179 Cost-aware design-time/run-time memory management methods and apparatus |
| 01/26/2006 | US20060018178 Circuit of sdram and method for data communication |
| 01/26/2006 | US20060018177 Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system |
| 01/26/2006 | US20060018176 Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system |
| 01/26/2006 | US20060018167 Flash memory device capable of reducing test time and test method thereof |
| 01/26/2006 | US20060017685 Single clock driven shift register and driving method for same |
| 01/26/2006 | DE10116639B4 Schreib/Lese-Abgleichschema zur Portverringerung in Mehrfachport-SRAM-Zellen Read / write port calibration scheme for reduction in multiple-port SRAM cells |