Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
06/2006
06/21/2006CN1260737C Memory module
06/20/2006US7065686 Dual port RAM
06/20/2006US7065003 Latency control circuit and method of latency control
06/20/2006US7065002 Memory device, memory device read method
06/20/2006US7065001 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
06/20/2006US7065000 Semiconductor memory device capable of stably setting mode register set and method therefor
06/20/2006US7064999 Digital memory circuit having a plurality of memory banks
06/20/2006US7064992 Method and apparatus for saving current in a memory device
06/20/2006US7064988 Synchronous semiconductor memory device of fast random cycle system and test method thereof
06/20/2006US7064987 Memory address generator with scheduled write and read address generating capability
06/20/2006US7064984 Circuit and method for reducing leakage current in a row driver circuit in a flash memory during a standby mode of operation
06/20/2006US7064975 Magnetic random access memory
06/20/2006US7064972 Ferroelectric memory device and read control method thereof
06/20/2006US7064589 Semiconductor device using two types of power supplies supplying different potentials
06/20/2006US7064453 Semiconductor memory device including a gate electrode with a recess
06/20/2006US7064373 Architecture and fabrication method of a vertical memory cell
06/20/2006US7063985 Method for fabricating sensor devices having improved switching properties
06/15/2006US20060129776 Method, system and memory controller utilizing adjustable read data delay settings
06/15/2006US20060126425 Delay-locked loop having a pre-shift phase detector
06/15/2006US20060126424 Phase-change memory device using chalcogenide compound as the material of memory cells
06/15/2006US20060126423 Memory element and memory device
06/15/2006US20060126422 Memory device and electronic device using the same
06/15/2006US20060126421 Apparatus and methods for generating a column select line signal in semiconductor memory device
06/15/2006US20060126420 Semiconductor memory
06/15/2006US20060126419 Method of configuring memory cell array block, method of addressing the same, semiconductor memory device and memory cell array block
06/15/2006US20060126418 Semiconductor memory device with hierarchical I/O line architecture
06/15/2006US20060126400 Semiconductor integrated circuit
06/14/2006EP1668671A2 Apparatus and method for selectively configuring a memory device using a bi-stable relay
06/14/2006EP1668646A1 Method and apparatus for implicit dram precharge
06/14/2006DE19549156B4 Datensignalverteilungsschaltung für ein Synchronspeicherelement Data signal distribution circuit for a synchronous memory device
06/14/2006DE10260344B4 Magnetische Dünnfilmspeichervorrichtung, die Daten mit bidirektionalem Strom schreibt Thin film magnetic memory device which writes data with bidirectional current
06/14/2006DE102005056369A1 Speicherrangdekoder für ein Dual-Inline-Speichermodul (DIMM) mit Mehrfachrang Memory rank decoder for a dual inline memory module (DIMM) with multiple Rank
06/14/2006DE102004009692B4 Halbleiterspeichervorrichtung A semiconductor memory device
06/14/2006CN1788321A Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM
06/14/2006CN1787110A Method and apparatus for realizing interface
06/14/2006CN1787109A Method for controlling data flowing of high speed memory body
06/14/2006CN1259624C Semiconductor device
06/13/2006US7062630 Storing device for writing data onto a plurality of installed storing mediums, storing control method for the storing device, and program thereof
06/13/2006US7061988 Interleaver memory access apparatus and method of mobile communication system
06/13/2006US7061941 Data input and output circuits for multi-data rate operation
06/13/2006US7061828 Fully-hidden refresh dynamic random access memory
06/13/2006US7061827 Semiconductor memory device
06/13/2006US7061826 Command decoder of semiconductor memory device
06/13/2006US7061825 Semiconductor integrated circuit
06/13/2006US7061824 Address buffer circuit for memory device
06/13/2006US7061823 Limited output address register technique providing selectively variable write latency in DDR2 (double data rate two) integrated circuit memory devices
06/13/2006US7061822 Clock generator for pseudo dual port memory
06/13/2006US7061813 Page buffer of non-volatile memory device and method of programming and reading non-volatile memory device
06/13/2006US7061803 Method and device for preserving word line pass bias using ROM in NAND-type flash memory
06/13/2006US7061799 Nonvolatile semiconductor memory device
06/13/2006US7061796 Thin film magnetic memory device for programming required information with an element similar to a memory cell information programming method
06/13/2006US7061792 Low AC power SRAM architecture
06/13/2006US7061783 Content addressable memory (CAM) capable of finding errors in a CAM cell array and a method thereof
06/13/2006US7061287 Delay locked loop
06/13/2006US7061267 Page boundary detector
06/13/2006CA2284154C Broadcast receiving system comprising a computer and a decoder
06/08/2006WO2005024833A3 A parallel asynchronous propagation pipeline structure to access multiple memory arrays
06/08/2006US20060120208 Delay-locked loop having a pre-shift phase detector
06/08/2006US20060120207 Method for controlling data output timing of memory device and device therefor
06/08/2006US20060120206 Apparatus for driving output signals from DLL circuit
06/08/2006US20060120205 Electro-resistance element and method of manufacturing the same
06/08/2006US20060120204 Dynamic monitoring of cell adhesion and spreading using the RT-CES system
06/08/2006US20060120203 Image display device and the driver circuit thereof
06/08/2006US20060120202 Data driver chip and light emitting display
06/08/2006US20060120201 Semiconductor memory device
06/08/2006US20060120200 Integrated DRAM memory device
06/08/2006US20060120156 Nonvolatile semiconductor memory device
06/07/2006EP1667159A2 Method and circuit for controlling generation of a boosted voltage in devices receiving dual supply voltages
06/07/2006EP1665280A2 Eeprom architecture and programming protocol
06/07/2006EP1665276A2 Defect-tolerant and fault-tolerant circuit interconnections
06/07/2006EP1665273A2 Method and apparatus for reading and writing to solid-state memory
06/07/2006CN1784852A Policy engine and methods and systems for protecting data
06/07/2006CN1783332A Reading and writing method of double speed dynamic random access memory
06/06/2006US7058874 Interleaver address generator and method of generating an interleaver address
06/06/2006US7058754 Nonvolatile memory device capable of simultaneous erase and program of different blocks
06/06/2006US7057971 Systems and methods that employ inductive current steering for digital logic circuits
06/06/2006US7057970 Nonvolatile ferroelectric memory and control device using the same
06/06/2006US7057969 Self-timed sneak current cancellation
06/06/2006US7057968 Semiconductor integrated circuit device
06/06/2006US7057967 Multi-mode synchronous memory device and methods of operating and testing same
06/06/2006US7057966 Semiconductor memory device for reducing current consumption in operation
06/06/2006US7057965 Method of performing access to a single-port memory device, memory access device, integrated circuit device and method of use of an integrated circuit device
06/06/2006US7057964 Semiconductor memory device with efficient multiplexing of I/O pad in multi-chip package
06/06/2006US7057963 Dual port SRAM memory
06/06/2006US7057962 Address control for efficient memory partition
06/06/2006US7057951 Semiconductor memory device for controlling write recovery time
06/06/2006US7057950 Semiconductor memory devices with delayed auto-precharge function and associated methods of auto-precharging semiconductor memory devices
06/06/2006US7057946 Semiconductor integrated circuit having latching means capable of scanning
06/06/2006US7057943 Data output controller for memory device
06/06/2006US7057942 Memory management device and memory device
06/06/2006US7057933 Non-volatile memory device with erase address register
06/06/2006US7057911 Memory structure, a system, and an electronic device, as well as a method in connection with a memory circuit
06/06/2006US7057866 System and method for disconnecting a portion of an integrated circuit
06/06/2006US7057441 Block selection circuit
06/06/2006US7056750 Ferroelectric film, method of manufacturing ferroelectric film, ferroelectric capacitor, and ferroelectric memory
06/01/2006US20060114742 Method and apparatus for optimizing strobe to clock relationship
06/01/2006US20060114741 Program invocation methods and devices utilizing the same
06/01/2006US20060114740 Ferroelectric memory and method of driving the same
06/01/2006US20060114739 Method and circuit for controlling generation of a boosted voltage in devices receiving dual supply voltages
06/01/2006US20060114738 Non-volatile semiconductor memory device
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