| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 09/21/2006 | US20060209615 Data reproduction device and method, and program |
| 09/21/2006 | US20060209614 Method of designing layout of semiconductor integrated circuit and apparatus for doing the same |
| 09/21/2006 | US20060209613 Memory modules and methods |
| 09/21/2006 | US20060209600 Simultaneous reading from and writing to different memory cells |
| 09/21/2006 | US20060209599 Nonvolatile semiconductor memory |
| 09/21/2006 | DE102005011892A1 Semiconductor memory element has memory cell field with groups of data items with set number of memory cells, has plurality of address lines whereby internal address lines is addressable to transferred binary coded memory address |
| 09/20/2006 | EP1702260A2 Memory card that supports file system interoperability |
| 09/20/2006 | EP1228510B1 Space management for managing high capacity nonvolatile memory |
| 09/19/2006 | US7111140 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
| 09/19/2006 | US7111122 Access circuit with various access data units |
| 09/19/2006 | US7111108 Memory system having a multiplexed high-speed channel |
| 09/19/2006 | US7110408 Method and apparatus for selecting a most signficant priority number for a device using a partitioned priority index table |
| 09/19/2006 | US7110322 Memory module including an integrated circuit device |
| 09/19/2006 | US7110321 Multi-bank integrated circuit memory devices having high-speed memory access timing |
| 09/19/2006 | US7110320 Nonvolatile semiconductor memory |
| 09/19/2006 | US7110319 Memory devices having reduced coupling noise between wordlines |
| 09/19/2006 | US7110318 Semiconductor memory device |
| 09/19/2006 | US7110315 Switch arrangement for switching a node between different voltages without generating combinational currents |
| 09/19/2006 | US7110313 Multiple-time electrical fuse programming circuit |
| 09/19/2006 | US7110309 Memory architecture with single-port cell and dual-port (read and write) functionality |
| 09/19/2006 | US7110286 Phase-change memory device and method of writing a phase-change memory device |
| 09/19/2006 | US7110282 Semiconductor memory device allowing accurate burn-in test |
| 09/19/2006 | US7110276 Integrated circuit memory devices reducing propagation delay differences between signals transmitted to separate spaced-apart memory blocks therein |
| 09/14/2006 | WO2006096783A1 Decoder for memory device |
| 09/14/2006 | US20060203684 Disc with temporary disc definition structure (TDDS) and temporary defect list (TDFL), and method of and apparatus for managing defect in the same |
| 09/14/2006 | US20060203670 Disc with temporary disc definition structure (TDDS) and temporary defect list (TDFL), and method of and apparatus for managing defect in the same |
| 09/14/2006 | US20060203669 Disc with temporary disc definition structure (TDDS) and temporary defect list (TDFL), and method of and apparatus for managing defect in the same |
| 09/14/2006 | US20060203668 Disc with temporary disc definition structure (TDDS) and temporary defect list (TDFL), and method of and apparatus for managing defect in the same |
| 09/14/2006 | US20060203638 Disc with temporary disc definition structure (TDDS) and temporary defect list (TDFL), and method of and apparatus for managing defect in the same |
| 09/14/2006 | US20060203635 Disc with temporary disc definition structure (TDDS) and temporary defect list (TDFL), and method of and apparatus for managing defect in the same |
| 09/14/2006 | US20060203607 Fully-hidden refresh dynamic random access memory |
| 09/14/2006 | US20060203606 System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal |
| 09/14/2006 | US20060203605 Multi-phase clock signal generator and method having inherently unlimited frequency capability |
| 09/14/2006 | US20060203604 Display device |
| 09/14/2006 | US20060203603 Memory arrangement and method for processing data |
| 09/14/2006 | US20060203602 Self-timed interface for strobe-based systems |
| 09/14/2006 | US20060203601 Memory device and method having programmable address configurations |
| 09/14/2006 | US20060203600 Low power word line control circuits with boosted voltage output for semiconductor memory |
| 09/14/2006 | US20060203599 Detection of row-to-row shorts and other row decode defects in memory devices |
| 09/14/2006 | US20060203598 Decoder for memory device |
| 09/14/2006 | US20060203597 Multiport memory device |
| 09/14/2006 | US20060203596 Semiconductor integrated circuit device |
| 09/14/2006 | US20060203595 Multiple memory device management |
| 09/14/2006 | US20060203577 Data output controller in semiconductor memory device and control method thereof |
| 09/14/2006 | DE102006007258A1 Memory address generation circuit for dynamic RAM used in mobile phone, controls select signals for column address strobe and row address strobe addresses, for memory mapping based on system configuration |
| 09/13/2006 | EP1701358A1 Data write-in method for flash memory |
| 09/13/2006 | EP1701355A2 Background operation for memory cells |
| 09/13/2006 | CN1833291A High density flash memory with high speed cache data interface |
| 09/13/2006 | CN1833289A Hub component for connection to one or more memory modules |
| 09/13/2006 | CN1832165A Stacked dram memory chip for a dual inline memory module (dimm) |
| 09/13/2006 | CN1832029A Semiconductor apparatus |
| 09/13/2006 | CN1832028A Multi-port memory based on dram core |
| 09/12/2006 | US7107507 Magnetoresistive solid-state storage device and data storage methods for use therewith |
| 09/12/2006 | US7107479 Apparatus and method for bidirectional transfer of data by a base station |
| 09/12/2006 | US7107476 Memory system using non-distributed command/address clock signals |
| 09/12/2006 | US7107394 Apparatus for capturing data on a debug bus |
| 09/12/2006 | US7106655 Multi-phase clock signal generator and method having inherently unlimited frequency capability |
| 09/12/2006 | US7106654 Arrangement comprising a memory device and a program-controlled unit |
| 09/12/2006 | US7106653 Semiconductor memory device and data read method of the same |
| 09/12/2006 | US7106652 Word line arrangement having multi-layer word line segments for three-dimensional memory array |
| 09/12/2006 | US7106651 Semiconductor memory device and method of reading data from semiconductor memory device |
| 09/12/2006 | US7106650 Semiconductor memory device |
| 09/12/2006 | US7106649 Semiconductor memory device |
| 09/12/2006 | US7106648 X-address extractor and memory for high speed operation |
| 09/12/2006 | US7106643 Method for manufacturing memory device provided with a defect recovery mechanism featuring a redundancy circuit |
| 09/12/2006 | US7106639 Defect management enabled PIRM and method |
| 09/12/2006 | US7106637 Asynchronous interface circuit and method for a pseudo-static memory device |
| 09/12/2006 | US7106636 Partitionable memory device, system, and method |
| 09/12/2006 | US7106633 Write pointer error recovery systems and methods |
| 09/12/2006 | US7106608 Priority circuit |
| 09/12/2006 | US7104459 Information storage apparatus and information processing apparatus using the same |
| 09/07/2006 | US20060198239 Modular numberical control |
| 09/07/2006 | US20060198238 Modified core for circuit module system and method |
| 09/07/2006 | US20060198237 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM |
| 09/07/2006 | US20060198236 Write address synchronization useful for a DDR prefetch SDRAM |
| 09/07/2006 | US20060198235 Distributed Delay-Locked-Based Clock and Data Recovery Systems |
| 09/07/2006 | US20060198234 Double data rate scheme for data output |
| 09/07/2006 | US20060198233 System and method to change data window |
| 09/07/2006 | US20060198232 Apparatus for memory device wordline |
| 09/07/2006 | US20060198231 Pulse controlled word line driver |
| 09/07/2006 | US20060198230 Memory device having terminals for transferring multiple types of data |
| 09/07/2006 | US20060198229 Memory device having terminals for transferring multiple types of data |
| 09/07/2006 | DE102006002888A1 Direktzugriffsspeicher mit niedriger Anfangslatenz Random access memory with low initial latency |
| 09/06/2006 | CN1828770A Efficient register for additive latency in ddr2 mode of operation |
| 09/06/2006 | CN1828767A Memory address generating circuit and memory controller using the same |
| 09/06/2006 | CN1828766A Multi-port memory based on dram core |
| 09/06/2006 | CN1274152C Signal generation and broadcasting |
| 09/05/2006 | US7103791 Interleaved delay line for phase locked and delay locked loops |
| 09/05/2006 | US7103738 Semiconductor integrated circuit having improving program recovery capabilities |
| 09/05/2006 | US7103690 Communication between logical macros |
| 09/05/2006 | US7103133 Register controlled delay locked loop circuit |
| 09/05/2006 | US7102960 Semiconductor memory device |
| 09/05/2006 | US7102959 Synchronous semiconductor memory device of fast random cycle system and test method thereof |
| 09/05/2006 | US7102957 Reduction of fusible links and associated circuitry on memory dies |
| 09/05/2006 | US7102956 Reduction of fusible links and associated circuitry on memory dies |
| 09/05/2006 | US7102955 Reduction of fusible links and associated circuitry on memory dies |
| 09/05/2006 | US7102947 Semiconductor memory device |
| 09/05/2006 | US7102940 Circuit arrangement for latency regulation |
| 09/05/2006 | US7102935 Semiconductor memory device driven with low voltage |
| 09/05/2006 | US7102386 Reconfigurable electronic device having interconnected data storage devices |