Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
08/2006
08/08/2006US7089465 Multi-port memory device having serial I/O interface
08/08/2006US7088803 Data access arrangement utilizing a serialized digital data path across an isolation barrier
08/08/2006US7088638 Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays
08/08/2006US7088637 Semiconductor memory device for high speed data access
08/08/2006US7088636 Semiconductor memory circuit
08/08/2006US7088629 Semiconductor memory device
08/08/2006US7088623 Non-volatile memory technology suitable for flash and byte operation application
08/08/2006US7088620 Nonvolatile semiconductor memory device
08/08/2006US7088607 Static memory cell and SRAM device
08/08/2006US7088604 Multi-bank memory
08/08/2006US7088186 High-frequency power amplifier module
08/03/2006WO2006081105A1 Memory block locking apparatus and methods
08/03/2006WO2005038864A3 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
08/03/2006US20060171247 Semiconductor memory module with bus architecture
08/03/2006US20060171246 Semiconductor memory device
08/03/2006US20060171245 Read and/or write detection system for an asynchronous memory array
08/03/2006US20060171244 Chip layout for multiple cpu core microprocessor
08/03/2006US20060171243 Memory array circuit with word line timing control for read operations and write operations
08/03/2006US20060171242 Semiconductor memory device and method of controlling sub word line driver thereof
08/03/2006US20060171241 Semiconductor memory device capable of selectively refreshing word lines
08/03/2006US20060171240 Bitline selection circuitry for nonvolatile memories
08/03/2006US20060171239 Dual Port Memory Unit Using a Single Port Memory Core
08/03/2006US20060171238 Semiconductor memory device
08/03/2006US20060171237 Semiconductor memory device
08/03/2006US20060171236 Semiconductor device
08/03/2006US20060171235 Non-volatile semiconductor memory device
08/03/2006US20060171234 DDR II DRAM data path
08/03/2006US20060171233 Near pad ordering logic
08/03/2006US20060171195 Semiconductor memory device
08/03/2006US20060170408 Method for activating and deactivating electronic circuit units and circuit arrangement for carrying out the method
08/03/2006DE10318625B4 Vertikale Speicherzelle und Verfahren zu deren Herstellung Vertical memory cell and process for their preparation
08/02/2006CN1811983A Semiconductor memory device and method of controlling sub word line driver thereof
08/02/2006CN1267928C Semiconductor memory device with control for auxiliary word lines for memory cell selection
08/01/2006US7085906 Memory device
08/01/2006US7085193 Clock-synchronous semiconductor memory device
08/01/2006US7085192 Semiconductor integrated circuit device
08/01/2006US7085191 Simulating a floating wordline condition in a memory device, and related techniques
08/01/2006US7085190 Variable boost voltage row driver circuit and method, and memory device and system including same
08/01/2006US7085189 Nonvolatile semiconductor storage device
08/01/2006US7085188 Semiconductor memory device, control method thereof, and control method of semiconductor device
08/01/2006US7085181 Semiconductor device having storage circuit which stores data in nonvolatile manner by using fuse element
08/01/2006US7085172 Data storage apparatus, data storage control apparatus, data storage control method, and data storage control program
08/01/2006US7085161 Non-volatile semiconductor memory with large erase blocks storing cycle counts
08/01/2006US7085156 Semiconductor memory device and method of operating same
07/2006
07/27/2006US20060165299 Semiconductor memory apparatus
07/27/2006US20060164910 Semiconductor memory device capable of performing page mode operation
07/27/2006US20060164909 System, method and storage medium for providing programmable delay chains for a memory system
07/27/2006US20060164908 Semiconductor memory device and a method of redressing a memory cell
07/27/2006US20060164907 Multiple flash memory device management
07/27/2006DE102006002522A1 Semiconductor memory device, has two wordline enable drivers generating enable signals on signal lines extending vertically and horizontally such that lines are shorter in length and are made of metal with smaller resistance
07/27/2006DE102005062533A1 Semiconductor memory device`s memory cell array block configuring method, involves dividing logic block with set of cells into sub-array blocks, and assigning portion of sub-array blocks to another logic block with another set
07/27/2006DE102005022768A1 Flash memory device transfers address signal to address comparator in 8-bit output mode, based on output mode decision signal and 8-bit forced decision signal
07/27/2006DE102004007661B4 Verfahren, Vorrichtung und Computerprogrammprodukt zur Optimierung eines Layouts von Versorgungsleitungen A method, apparatus and computer program product for optimization of a layout of power supply lines
07/26/2006EP1684306A2 Phase change memory device and data writing method
07/26/2006EP1684303A1 Pulse controlled word line driver
07/25/2006US7082491 Memory device having different burst order addressing for read and write operations
07/25/2006US7082077 Control method of semiconductor memory device and semiconductor memory device
07/25/2006US7082076 Memory module with hierarchical functionality
07/25/2006US7082075 Memory device and method having banks of different sizes
07/25/2006US7082074 Semiconductor device having a power down mode
07/25/2006US7082067 Circuit for verifying the write speed of SRAM cells
07/25/2006US7082063 Semiconductor memory device
07/25/2006US7082062 Voltage output control apparatus and method
07/25/2006US7082050 Method to equalize word current circuitry
07/25/2006US7082048 Low voltage operation DRAM control circuits
07/20/2006US20060161876 Array-based architecture for molecular electronics
07/20/2006US20060161743 Intelligent memory array switching logic
07/20/2006US20060158955 Semiconductor memory device
07/20/2006US20060158954 Semiconductor memory device, system with semiconductor memory device, and method for operating a semiconductor memory device
07/20/2006US20060158953 Logic circuit and word-driver circuit
07/20/2006US20060158952 SRAM device capable of performing burst operation
07/19/2006CN1265462C Semiconductor storage device
07/19/2006CN1265394C Addressing method of memory matrix
07/18/2006US7080199 Method to maintain data integrity during flash file transfer to raid controller flash using a terminal emulation program
07/18/2006US7080192 File storage and erasure in flash memory
07/18/2006US7079447 Dynamical adaptation of memory sense electronics
07/18/2006US7079446 DRAM interface circuits having enhanced skew, slew rate and impedance control
07/18/2006US7079444 Memory system using simultaneous bi-directional input/output circuit on an address bus line
07/18/2006US7079443 Semiconductor device
07/18/2006US7079440 Method and system for providing directed bank refresh for volatile memories
07/18/2006US7079432 Semiconductor storage device formed to optimize test technique and redundancy technology
07/18/2006US7079431 Arrangement with a memory for storing data
07/18/2006US7079426 Dynamic multi-Vcc scheme for SRAM cell stability control
07/18/2006US7079417 Read-while-write flash memory devices having local row decoder circuits activated by separate read and write signals
07/18/2006US7078953 Level down converter
07/18/2006US7078762 Semiconductor memory device and method for producing the same
07/13/2006US20060152994 Timer lockout circuit for synchronous applications
07/13/2006US20060152993 Electronic apparatus
07/13/2006US20060152992 Semiconductor memory device having wordline enable signal line and method of arranging the same
07/13/2006US20060152980 Low-power delay buffer circuit
07/13/2006US20060152979 Semiconductor memory device
07/13/2006DE112004001660T5 Echotakt auf Speichersystem mit Warteinformationen Echo clock on storage system with waiting information
07/13/2006DE102006000883A1 Integrated circuit memory device e.g. RAM, operating method, involves executing read command within memory device concurrently by providing write address and write command to device prior to terminating execution of read command
07/13/2006DE102005048850A1 Speichervorrichtung und Verfahren zum Empfangen von Instruktionsdaten Memory device and method for receiving instruction data
07/12/2006EP1679894A2 Broadcast and reception system, and conditional access system therefor
07/12/2006EP1678622A2 Circulator chain memory command and address bus topology
07/12/2006EP1364372B1 Non-destructive readout
07/12/2006CN1802738A Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits
07/12/2006CN1801397A 半导体存储器件 A semiconductor memory device
07/12/2006CN1801389A High performance register file with bootstrapped storage supply and related method
1 ... 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 ... 194