| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 02/15/2007 | US20070035336 Clock generating circuit with multiple modes of operation |
| 02/15/2007 | DE102005036267A1 Memory assembly for reducing power loss in integrated circuits e.g. for mobile radio subscriber units, has many switching units whereby data word is fed to input side of switching unit to which memory element is connected |
| 02/14/2007 | EP1634296A4 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same |
| 02/14/2007 | EP0974229B8 Broadcast and reception system, and conditional access system therefor |
| 02/13/2007 | US7178113 Identification of an integrated circuit from its physical manufacture parameters |
| 02/13/2007 | US7178039 Method and arrangement for the verification of NV fuses as well as a corresponding computer program product and a corresponding computer-readable storage medium |
| 02/13/2007 | US7178012 Semiconductor device |
| 02/13/2007 | US7178001 Semiconductor memory asynchronous pipeline |
| 02/13/2007 | US7177998 Method, system and memory controller utilizing adjustable read data delay settings |
| 02/13/2007 | US7177385 Shift register for safely providing a configuration bit |
| 02/13/2007 | US7177231 Selectable clock input |
| 02/13/2007 | US7177230 Memory controller and memory system |
| 02/13/2007 | US7177229 Apparatus for tuning a RAS active time in a memory device |
| 02/13/2007 | US7177228 Apparatus and method for controlling enable time of signal controlling operation of data buses of memory device |
| 02/13/2007 | US7177227 Transistor layout configuration for tight-pitched memory array lines |
| 02/13/2007 | US7177226 Word line driving circuit of semiconductor memory device |
| 02/13/2007 | US7177224 Controlling multiple signal polarity in a semiconductor device |
| 02/13/2007 | US7177223 Memory device and method having banks of different sizes |
| 02/13/2007 | US7177219 Disabling clocked standby mode based on device temperature |
| 02/13/2007 | US7177214 Methods and systems for dynamically selecting word line off times and/or bit line equalization start times in memory devices |
| 02/13/2007 | US7177209 Semiconductor memory device and method of driving the same |
| 02/13/2007 | US7177206 Power supply circuit for delay locked loop and its method |
| 02/13/2007 | US7177204 Pulse width adjusting circuit for use in semiconductor memory device and method therefor |
| 02/13/2007 | US7177202 Method for accessing a single port memory |
| 02/13/2007 | US7177197 Latched programming of memory and method |
| 02/13/2007 | US7177193 Programmable fuse and antifuse and method therefor |
| 02/13/2007 | US7177183 Multiple twin cell non-volatile memory array and logic block structure and method therefor |
| 02/13/2007 | US7177181 Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics |
| 02/13/2007 | US7177169 Word line arrangement having multi-layer word line segments for three-dimensional memory array |
| 02/13/2007 | US7176041 PAA-based etchant, methods of using same, and resultant structures |
| 02/08/2007 | WO2007015773A2 Memory device and method having multiple address, data and command buses |
| 02/08/2007 | WO2006130763A3 Partial page scheme for memory technologies |
| 02/08/2007 | US20070030755 Apparatus for testing a nonvolatile memory and a method thereof |
| 02/08/2007 | US20070030754 Initialization scheme for a reduced-frequency, fifty percent duty cycle corrector |
| 02/08/2007 | US20070030753 Seamless coarse and fine delay structure for high performance DLL |
| 02/08/2007 | US20070030751 Semiconductor memory having a short effective word line cycle time and method for reading data from a semiconductor memory of this type |
| 02/08/2007 | US20070030048 Voltage Switching Circuit |
| 02/07/2007 | EP1750273A1 Memory cell with increased access reliability |
| 02/07/2007 | CN1299298C Circuit device for semiconductor |
| 02/06/2007 | US7173878 Apparatus for driving output signals from DLL circuit |
| 02/06/2007 | US7173877 Memory system with two clock lines and a memory device |
| 02/06/2007 | US7173876 Semiconductor integrated circuit |
| 02/06/2007 | US7173875 SRAM array with improved cell stability |
| 02/06/2007 | US7173874 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface |
| 02/06/2007 | US7173872 Method and apparatus for controlling a high voltage generator in a wafer burn-in test |
| 02/06/2007 | US7173871 Semiconductor memory device and method of outputting data strobe signal thereof |
| 02/06/2007 | US7173867 Memory redundancy circuit techniques |
| 02/06/2007 | US7173866 Circuit for generating data strobe signal in DDR memory device, and method therefor |
| 02/06/2007 | US7173858 Nonvolatile memory and method of driving the same |
| 02/06/2007 | US7173853 Nonvolatile semiconductor memory |
| 02/06/2007 | US7173837 Content addressable memory (CAM) cell bit line architecture |
| 02/06/2007 | US7173610 Decoder system capable of performing a plural-stage process |
| 02/06/2007 | US7173300 Magnetoresistive element, method for making the same, and magnetic memory device incorporating the same |
| 02/01/2007 | WO2006105453A3 Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers |
| 02/01/2007 | US20070025175 Reducing read data strobe latency in a memory system |
| 02/01/2007 | US20070025174 Dual port semiconductor memory device |
| 02/01/2007 | US20070025173 Memory device and method having multiple address, data and command buses |
| 02/01/2007 | US20070025150 Flash memory device capable of preventing program disturbance according to partial programming |
| 02/01/2007 | US20070025137 Dynamic memory word line driver scheme |
| 02/01/2007 | DE102005033473A1 Speicheranordnung und Verfahren zum Betrieb einer Speicheranordnung Memory device and method of operating a memory array |
| 02/01/2007 | DE10156272B4 Multi-Chip-Speichervorrichtung und Speichermodul mit einer unabhängigen Steuerung der Speicherchips The multi-chip memory module and memory device with an independent control of the memory chips |
| 01/31/2007 | EP1747560A1 Latched programming of memory and method |
| 01/31/2007 | EP1747559A2 Method and apparatus for a dual power supply to embedded non-volatile memory |
| 01/31/2007 | CN1906700A NAND memory array incorporating multiple series selection devices and method for operation of same |
| 01/31/2007 | CN1906697A Method for operating a data storage apparatus employing passive matrix addressing |
| 01/31/2007 | CN1905059A Multi-port memory based on DRAM core |
| 01/31/2007 | CN1904854A Stream data buffer unit and access method thereof |
| 01/30/2007 | US7171571 Robotic data storage library with soft power on/off capability |
| 01/30/2007 | US7171323 Integrated circuit having clock trim circuitry |
| 01/30/2007 | US7170819 Integrated semiconductor memory device for synchronizing a signal with a clock signal |
| 01/30/2007 | US7170818 Semiconductor memory device and module for high frequency operation |
| 01/30/2007 | US7170817 Access of two synchronous busses with asynchronous clocks to a synchronous single port ram |
| 01/30/2007 | US7170816 Method and apparatus for passing charge from word lines during manufacture |
| 01/30/2007 | US7170815 Memory apparatus having multi-port architecture for supporting multi processor |
| 01/30/2007 | US7170814 Multi-port semiconductor memory |
| 01/30/2007 | US7170808 Power saving refresh scheme for DRAMs with segmented word line architecture |
| 01/30/2007 | US7170800 Low-power delay buffer circuit |
| 01/30/2007 | US7170792 Semiconductor device |
| 01/30/2007 | US7170325 Circuit for controlling a delay time of input pulse and method of controlling the same |
| 01/25/2007 | US20070020859 Method of making non-volatile field effect devices and arrays of same |
| 01/25/2007 | US20070019497 Semiconductor memory device |
| 01/25/2007 | US20070019496 Semiconductor memory device for stably controlling power mode at high frequency and method of controlling power mode thereof |
| 01/25/2007 | US20070019495 Address decoding systems and methods |
| 01/25/2007 | US20070019494 Semiconductor memory module with bus architecture |
| 01/25/2007 | US20070019489 Disabling clocked standby mode based on device temperature |
| 01/25/2007 | US20070019488 Temperature update masking to ensure correct measurement of temperature when references become unstable |
| 01/25/2007 | US20070019467 Semiconductor memory device |
| 01/24/2007 | EP1746496A1 Modulo arithmetic |
| 01/24/2007 | EP1535162A4 Memory device supporting a dynamically configurable core organisation |
| 01/24/2007 | CN1902708A Circuit and method for controlling a clock synchronizing circuit for low power refresh operation |
| 01/24/2007 | CN1901090A Storage and reproduction apparatus |
| 01/24/2007 | CN1296832C Destructive-read random access memory system buffered with destructive-read memory cache |
| 01/23/2007 | US7168005 Programable multi-port memory BIST with compact microcode |
| 01/23/2007 | US7167946 Method and apparatus for implicit DRAM precharge |
| 01/23/2007 | US7167944 Block management for mass storage |
| 01/23/2007 | US7167411 Apparatus for testing a nonvolatile memory and a method thereof |
| 01/23/2007 | US7167410 Memory system and memory device having a serial interface |
| 01/23/2007 | US7167409 Semiconductor memory device |
| 01/23/2007 | US7167407 Dynamic semiconductor memory device and power saving mode of operation method of the same |
| 01/23/2007 | US7167406 Image display device and driving method thereof |