Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
01/2007
01/23/2007US7167388 Integrated circuit and method for operating an integrated circuit
01/18/2007WO2007008325A2 Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations
01/18/2007WO2005034176A3 Apparatus and method for selectively configuring a memory device using a bi-stable relay
01/18/2007WO2004051704A3 System and method for expanding a pulse width
01/18/2007US20070014184 Wordline decoder of non-volatile memory device using hpmos
01/18/2007US20070014183 Nonvolatile semiconductor memory device in which write and erase threshold voltages are set at levels symmetrical about neutral threshold voltage of cell transistor
01/18/2007US20070014182 Nonvolatile semiconductor memory device which reads by decreasing effective threshold voltage of selector gate transistor
01/18/2007US20070014181 Semiconductor memory device having connected bit lines and data shift method thereof
01/18/2007US20070014180 Device and method for selecting 1-row and 2-row activation
01/18/2007US20070014179 Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations
01/18/2007US20070014175 DRAM and method for partially refreshing memory cell array
01/18/2007US20070014150 Phase change random access memory (PRAM) device having variable drive voltages
01/17/2007EP1743446A1 Policy engine and methods and systems for protecting data
01/17/2007CN1898744A Low voltage operation dram control circuits
01/17/2007CN1295706C Non-volatile memory, recording apparatus and recording method
01/17/2007CN1295617C Data storage apparatus, data storage control apparatus, data storage control method, and data storage control program
01/16/2007US7164617 Memory control apparatus for synchronous memory unit with switched on/off clock signal
01/16/2007US7164616 Memory array leakage reduction circuit and method
01/16/2007US7164303 Delay circuit, ferroelectric memory device and electronic equipment
01/16/2007US7164294 Method for forming programmable logic arrays using vertical gate transistors
01/16/2007US7163755 Magneto-resistive element
01/11/2007US20070008810 Clock-independent mode register setting methods and apparatuses
01/11/2007US20070008809 Semiconductor memory device having different synchronzing timings depending on the value of CAS latency
01/11/2007US20070008808 Dram memory
01/11/2007US20070008807 Wordline driver
01/11/2007US20070008806 Word line decoder suitable for low operating voltage of flash memory device
01/11/2007US20070008805 Circuit and method of driving a word line of a memory device
01/11/2007US20070008804 High voltage wordline driver with a three stage level shifter
01/11/2007US20070008792 Circuitry and method for adjusting signal length
01/11/2007US20070008791 DQS strobe centering (data eye training) method
01/11/2007US20070008789 Control circuit for stable exit from power-down mode
01/11/2007US20070008787 Output circuit and method thereof
01/11/2007US20070008771 Tracking circuit for a memory device
01/10/2007EP1609153B1 Simultaneous reading from and writing to different memory cells
01/10/2007CN1892914A Circuit and method for driving word line
01/10/2007CN1892903A 半导体存储器 Semiconductor memory
01/10/2007CN1892896A Semiconductor memory module with bus architecture
01/10/2007CN1294596C Magnetic random access memory and readout method and manufacturing method
01/09/2007US7162592 Method for bus capacitance reduction
01/09/2007US7161870 Synchronous flash memory command sequence
01/09/2007US7161869 Transmission device
01/09/2007US7161868 Multiport semiconductor memory device capable of sufficiently steadily holding data and providing a sufficient write margin
01/09/2007US7161867 Semiconductor memory device
01/09/2007US7161866 Memory device tester and method for testing reduced power states
01/09/2007US7161865 Semiconductor device
01/09/2007US7161864 Bit refresh circuit for refreshing register bit values, integrated circuit device having the same, and method of refreshing register bit values
01/09/2007US7161853 Circuit for accessing word line of semiconductor device and method of accessing word line using the same
01/09/2007US7161847 Data input/output (I/O) apparatus for use in memory device
01/09/2007US7161824 Method for programming a memory arrangement and programmed memory arrangement
01/09/2007US7161820 Memory module and memory system having an expandable signal transmission, increased signal transmission and/or high capacity memory
01/09/2007US7161218 One-time programmable, non-volatile field effect devices and methods of making same
01/08/2007CA2550963A1 Devices containing multi-bit data
01/04/2007WO2007002509A2 Word line driver for dram embedded in a logic process
01/04/2007US20070002676 Buffered continuous multi-drop clock ring
01/04/2007US20070002675 Synchronous memory device with output driver controller
01/04/2007US20070002674 Semiconductor memory device having improved column selection lines and method of driving the same
01/04/2007US20070002673 Memory array leakage reduction circuit and method
01/04/2007US20070002672 Semiconductor memory device
01/04/2007US20070002671 Integrated circuit device and electronic instrument
01/04/2007US20070002670 Integrated circuit device and electronic instrument
01/04/2007US20070002669 Integrated circuit device and electronic instrument
01/04/2007US20070002668 Micro-tile memory interfaces
01/04/2007US20070002667 Integrated circuit device and electronic instrument
01/03/2007EP1739683A1 Space management for managing high capacity nonvolatile memory
01/03/2007EP1738373A1 Addressing data within dynamic random access memory
01/03/2007EP1738371A1 Collision detection in a multi-port memory system
01/02/2007US7159124 Non-volatile semiconductor memory that prevents unauthorized reading
01/02/2007US7158444 Semiconductor memory device
01/02/2007US7158443 Delay-lock loop and method adapting itself to operate over a wide frequency range
01/02/2007US7158442 Flexible latency in flash memory
01/02/2007US7158441 Semiconductor integrated circuit
01/02/2007US7158440 FIFO memory devices having write and read control circuits that support x4N, x2N and xN data widths during DDR and SDR modes of operation
01/02/2007US7158439 Memory and driving method of the same
01/02/2007US7158438 Network packet buffer allocation optimization in memory bank systems
01/02/2007US7158437 Memory control device and memory control method
01/02/2007US7158436 Semiconductor memory devices
01/02/2007US7158432 Memory with robust data sensing and method for sensing data
01/02/2007US7158426 Method for testing an integrated semiconductor memory
01/02/2007US7158424 Semiconductor memory device
01/02/2007US7158405 Semiconductor memory device having a plurality of memory areas with memory elements
12/2006
12/28/2006WO2006138003A1 Memory data access scheme
12/28/2006WO2005125015A3 Method and apparatus for time measurement
12/28/2006US20060294322 Multi-port memory based on DRAM core
12/28/2006US20060291323 Parallel data path architecture
12/28/2006US20060291322 Circuit and method for retrieving data stored in semiconductor memory cells
12/28/2006US20060291321 Word line driver for DRAM embedded in a logic process
12/28/2006US20060291311 Memory device for retaining data during power-down mode and method of operating the same
12/28/2006US20060291306 Semiconductor memory device
12/28/2006US20060291300 High speed data access memory arrays
12/28/2006US20060291297 Semiconductor memory
12/28/2006US20060290395 Digital DLL device, digital DLL control method, and digital DLL control program
12/28/2006DE19929172B4 Integrierter Speicher Built-in Memory
12/27/2006EP1736994A1 Stacked memories with improved addressing means for microprocessor
12/27/2006EP1736993A1 Magnetic random access memory array having bit/word lines for shared write select and read operations
12/27/2006EP1114461B1 Semiconductor circuit
12/27/2006CN1886797A Memory device having multiple array structure for increased bandwidth
12/26/2006US7154905 Method and system for nesting of communications packets
12/26/2006US7154810 Synchronous controlled, self-timed local SRAM block
12/26/2006US7154809 Method for measuring the delay time of a signal line
12/26/2006US7154808 Semiconductor memory device for simultaneously testing blocks of cells
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