Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
06/2007
06/28/2007US20070147165 Memory unit and semiconductor device
06/28/2007US20070147164 Row decoder for preventing leakage current and semiconductor memory device including the same
06/28/2007US20070147163 Address decoder, storage device, processor device, and address decoding method for the storage device
06/28/2007US20070147162 Multi-port semiconductor memory device having variable access paths and method therefor
06/28/2007US20070147161 Semiconductor memory device having layout for minimizing area of sense amplifier region and word line driver region
06/28/2007US20070147160 Semiconductor Device
06/28/2007US20070147155 Memory Device Having a Configurable Oscillator for Refresh Operation
06/28/2007US20070147152 Sense amplifier for semiconductor memory device
06/28/2007US20070147148 Semiconductor memory device
06/28/2007DE10224283B4 Verfahren zur Speichersteuerung A process for the memory controller
06/28/2007DE10121708B4 Halbleiterspeichereinrichtung und Verfahren zum Ändern von Ausgangsdaten dieser Einrichtung Semiconductor memory device and method of changing output data of this institution
06/27/2007EP1800311A1 Multi-column addressing mode memory system including an intergrated circuit memory device
06/27/2007CN1989569A Dram with half and full density operation
06/27/2007CN1988035A 多路可存取半导体存储器器件 Multiple accessible semiconductor memory device
06/26/2007US7236425 Charge pump circuit
06/26/2007US7236424 Semiconductor memory device
06/26/2007US7236423 Low power multi-chip semiconductor memory device and chip enable method thereof
06/26/2007US7236422 Image display device and the driver circuit thereof
06/26/2007US7236421 Read-modify-write memory using read-or-write banks
06/26/2007US7236420 Memory chip architecture having non-rectangular memory banks and method for arranging memory banks
06/26/2007US7236378 Signal distribution to a plurality of circuit units
06/26/2007US7236022 Device and method for setting an initial value
06/21/2007WO2007002509A3 Word line driver for dram embedded in a logic process
06/21/2007US20070143677 Independent link and bank selection
06/21/2007US20070140040 Memory module
06/21/2007US20070140039 Nonvolatile semiconductor memory
06/21/2007US20070140038 Selectable memory word line deactivation
06/21/2007US20070140037 Line driver circuit and method with standby mode of operation
06/21/2007US20070140036 Semiconductor memory device
06/21/2007US20070140035 Apparatus and Method for Pipelined Memory Operations
06/21/2007US20070139995 Semiconductor memory device
06/21/2007DE4332583B4 Schaltung zum Klemmen eines Freigabetaktsignales für eine Halbleiterspeichervorrichtung Circuit for clamping an enable clock signal for a semiconductor memory device
06/21/2007DE19921232B4 Verfahren zum gesicherten Schreiben eines Zeigers für einen Ringspeicher, zugehöriger Ringspeicher, Verwendung des Ringspeichers und Chipkarte mit Ringspeicher Method for the secure writing a pointer to a ring buffer, related storage ring, using the ring memory and chip card with circular buffer
06/21/2007DE102005036267B4 Speicheranordnung und Verfahren zum Adressieren einer Speicheranordnung Memory device and method of addressing a memory array
06/21/2007DE10046051B4 Nichtflüchtiger ferroelektrischer Speicher und Schaltung zum Betreiben desselben Of the same non-volatile ferroelectric memory and circuit for operating
06/20/2007CN1983452A Multiport semiconductor memory device
06/20/2007CN1983442A 译码器电路 Decoder circuit
06/20/2007CN1983441A 半导体集成电路设备 The semiconductor integrated circuit device
06/20/2007CN1322513C Dynamic semiconductor memory and semiconductor IC device
06/20/2007CN1322512C Memory device and method for operation of the same
06/19/2007US7233543 System and method to change data window
06/19/2007US7233542 Method and apparatus for address generation
06/19/2007US7233541 Storage device
06/19/2007US7233540 Latch-based random access memory (LBRAM) with tri-state banking and contention avoidance
06/19/2007US7233532 Reconfiguration port for dynamic reconfiguration-system monitor interface
06/19/2007US7233180 Circuits and methods of temperature compensation for refresh oscillator
06/14/2007US20070133339 Data interface device for accessing memory
06/14/2007US20070133338 Clock recovery circuit and a memory device employing the same
06/14/2007US20070133337 Semiconductor storage device
06/14/2007US20070133290 Semiconductor memory device equipped with storage section for storing setting information to set initial operation and function
06/14/2007DE10107427B4 Halbleiterspeichervorrichtung A semiconductor memory device
06/13/2007CN1981275A Method and device for managing a bus
06/12/2007US7231487 Automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards
06/12/2007US7230876 Register read for volatile memory
06/12/2007US7230875 Delay locked loop for use in synchronous dynamic random access memory
06/12/2007US7230874 Semiconductor storage device
06/12/2007US7230873 Forced pulldown of array read bitlines for generating MUX select signals
06/07/2007WO2007065090A2 Pseudo-dynamic word-line driver
06/07/2007WO2006065922A3 Substitution of defective readout circuits in imagers
06/07/2007WO2006036413A3 System and method for storing data
06/07/2007US20070130400 Providing services from a remote computer system to a user station over a communications network
06/07/2007US20070127306 Memory architecture having multiple partial wordline drivers and contacted and feed-through bitlines
06/07/2007US20070127305 Semiconductor memory
06/07/2007US20070127304 Memory module and register with minimized routing path
06/07/2007US20070127299 Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same
06/07/2007US20070127295 Nonvolatile semiconductor memory
06/07/2007US20070127280 Deterministic addressing of nanoscale devices assembled at sublithographic pitches
06/06/2007EP1214713B1 Architecture, method(s) and circuitry for low power memories
06/06/2007DE19650715B4 Unterwortleitungstreiberschaltung und diese verwendende Halbleiterspeichervorrichtung Sub-word line driver circuit, and this semiconductor memory device used
06/06/2007DE102004026808B4 Abwärtskompatibler Speicherbaustein Compatible memory module downward
06/06/2007CN1975922A Semiconductor storage device
06/06/2007CN1975921A Circuit arrangement for generating an n-bit output pointer, semiconductor memory and method
06/06/2007CN1975634A Adaptive throttling of memory accesses, such as throttling RDRAM accesses in a real-time system
06/06/2007CN1320517C Device comprising array of pixels allowing storage of data
06/05/2007US7227812 Write address synchronization useful for a DDR prefetch SDRAM
06/05/2007US7227811 Address latch signal generation circuit and address decoding circuit
06/05/2007US7227810 Semiconductor device and testing method for semiconductor device
06/05/2007US7227809 Clock generator having a delay locked loop and duty cycle correction circuit in a parallel configuration
06/05/2007US7227808 Semiconductor memory device which compensates for delay time variations of multi-bit data
06/05/2007US7227807 Method of configuring memory cell array block, method of addressing the same, semiconductor memory device and memory cell array block
06/05/2007US7227806 High speed wordline decoder for driving a long wordline
06/05/2007US7227805 Semiconductor memory device having a global data bus
06/05/2007US7227801 Semiconductor memory device with reliable fuse circuit
06/05/2007US7227792 Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same
06/05/2007US7227791 Semiconductor memory device including circuit to store access data
06/05/2007US7227788 Memory management device and memory device
06/05/2007US7227251 Semiconductor device and a memory system including a plurality of IC chips in a common package
05/2007
05/31/2007WO2007061710A1 Uni-stage delay speculative address decoder
05/31/2007US20070121420 Page access circuit of semiconductor memory device
05/31/2007US20070121419 Alignment of memory read data and clocking
05/31/2007US20070121418 Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device
05/31/2007US20070121417 Memory array decoder
05/31/2007US20070121416 Memory array decoder
05/31/2007US20070121415 Pseudo-dynamic word-line driver
05/31/2007US20070121413 Apparatus and method of controlling bank of semiconductor memory
05/31/2007US20070121412 Uni-stage delay speculative address decoder
05/31/2007US20070121405 Semiconductor memory device
05/31/2007US20070121364 One-time programmable, non-volatile field effect devices and methods of making same
05/31/2007DE102006054161A1 Eingebettete Testschaltung zum Testen eines Dual-Port-Speichers Embedded test circuit for testing a dual-port memory
05/30/2007EP1661137A4 Low voltage operation dram control circuits
1 ... 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 ... 194