Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
04/2007
04/05/2007US20070076507 Storage device employing a flash memory
04/05/2007US20070076496 Image display device and driving method thereof
04/05/2007DE10310779B4 Integrierte Speicherschaltung mit erhöhter Zuverlässigkeit The integrated memory circuit with increased reliability
04/05/2007DE102006030374A1 Interner Signalgenerator zur Verwendung in einer Halbleiterspeichereinrichtung Internal signal generator for use in a semiconductor memory device
04/05/2007DE102006030373A1 Halbleiterspeichervorrichtung A semiconductor memory device
04/05/2007DE102005046364A1 Integrated semiconductor memory e.g. double data rate synchronous dynamic random access memory, for mobile telephone, has selection circuit controlled by address storage unit, which stores data for selecting memory cells
04/05/2007DE102005045311A1 Dynamic random access memory has bit line switch maintained in conductive state for long time based on read or write mode, to switch ON or OFF sense amplifier
04/05/2007DE102004011672B4 Vorrichtung zur Datensynchronisation Apparatus for data synchronization
04/04/2007CN1941363A Information transfer in electronic modules and device with corresponding structure
04/04/2007CN1941174A Multi-port memory device
04/04/2007CN1308961C Semiconductor storage device
04/04/2007CN1308906C Liquid crystal display device
04/03/2007US7200068 Multi-ported register files
04/03/2007US7200061 Sense amplifier for semiconductor memory device
04/03/2007US7200055 Memory module with termination component
04/03/2007US7199648 Semiconductor integrated circuit including first and second switching transistors having operation states corresponding to operation states of first and second logic circuits
04/03/2007US7199634 Duty cycle correction circuits suitable for use in delay-locked loops and methods of correcting duty cycles of periodic signals
04/03/2007US7199631 Storing an unchanging binary code in an integrated circuit
04/03/2007US7199605 Method and apparatus for low capacitance, high output impedance driver
03/2007
03/29/2007US20070073846 Software distribution over a network
03/29/2007US20070073845 Content distribution over a network
03/29/2007US20070070800 Externally worn vasovagal syncope detection device
03/29/2007US20070070799 Memory and method of controlling access to memory
03/29/2007US20070070798 Internal address generator for use in semiconductor memory device
03/29/2007US20070070797 Data transmission device in semiconductor memory device
03/29/2007US20070070796 Semiconductor memory device having data-compress test mode
03/29/2007US20070070795 Multi-port memory device with serial input/output interface
03/29/2007US20070070794 Arbitration for memory device with commands
03/29/2007US20070070793 Semiconductor memory device
03/29/2007US20070070792 Output controller with test unit
03/29/2007US20070070791 Clock control device
03/29/2007US20070070790 Output control device
03/29/2007US20070070789 Module apparatus and method for controlling auto on/off of clock for saving power
03/29/2007US20070070788 Apparatus and method for dynamically controlling data transfer in memory device
03/29/2007US20070070787 Semiconductor memory device
03/29/2007US20070070786 Semiconductor storage device
03/29/2007US20070070785 Semiconductor memory device
03/29/2007US20070070784 Sense amplifier over driver control circuit and method for controlling sense amplifier of semiconductor device
03/29/2007US20070070783 Semiconductor memory device
03/29/2007US20070070782 Memory device input buffer, related memory device, controller and system
03/29/2007US20070070781 Internal address generator
03/29/2007US20070070780 Output driving device
03/29/2007US20070070779 Multi-port semiconductor memory
03/29/2007US20070070778 Multi-port memory device with serial input/output interface
03/29/2007US20070070777 Semiconductor memory device
03/29/2007US20070070776 Semiconductor memory device
03/29/2007US20070070775 Device for driving global signal
03/29/2007US20070070774 Memory device having latch for charging or discharging data input/output line
03/29/2007US20070070716 Semiconductor integrated circuit device
03/29/2007US20070070692 Compressed Event Counting Technique and Application to a Flash Memory System
03/29/2007DE4439661C5 Wortleitungstreiberschaltkreis für eine Halbleiterspeichereinrichtung Wordline driver circuit for a semiconductor memory device
03/29/2007DE19846264B4 Speicherzelleneinheit für einen nichtflüchtigen ferroelektrischen Speicher, nichtflüchtiger ferroelektrischer Speicher mit einer Vielzahl dieser Zellen, Wortleitungstreiber für denselben sowie Verfahren zur Herstellung dieser Zellen Memory cell unit for a nonvolatile ferroelectric memory, non-volatile ferroelectric memory having a plurality of these cells, word line drivers for the same, and methods for producing these cells
03/28/2007CN1307647C DRAM, memory, and method for executing read command
03/27/2007US7196968 Method of driving data lines, and display device and liquid crystal display device using method
03/27/2007US7196967 Semiconductor integrated circuit
03/27/2007US7196966 On die termination mode transfer circuit in semiconductor memory device and its method
03/27/2007US7196965 Over driving control signal generator in semiconductor memory device
03/27/2007US7196964 Selectable memory word line deactivation
03/27/2007US7196963 Address isolation for user-defined configuration memory in programmable devices
03/27/2007US7196962 Packet addressing programmable dual port memory devices and related methods
03/27/2007US7196961 Memory control device
03/22/2007US20070064517 Output control signal generating circuit
03/22/2007US20070064516 Methods and apparatus for lancet actuation
03/22/2007US20070064515 Reconfigurable input/output in hierarchical memory link
03/22/2007DE102006041646A1 Schaltung und Verfahren zur Sperrvorspannungserzeugung und Pegeldetektor hierfür Circuit and method for Sperrvorspannungserzeugung and level detector therefor
03/22/2007DE102006007023B3 Semiconductor memory device e.g. flash memory, has sector control simultaneously controlling wordlines and connected to wordlines, where control has programmable sector memory for storing of sectors and wordlines, and belongs to sectors
03/21/2007CN1934528A Memory card that supports file system interoperability
03/20/2007US7193929 Semiconductor integrated circuit
03/20/2007US7193928 Signal output device and method for the same
03/20/2007US7193927 Memory device and method having banks of different sizes
03/20/2007US7193926 Memory device for reducing leakage current
03/20/2007US7193925 Low power semiconductor memory device
03/20/2007US7193924 Dual-port static random access memory having improved cell stability and write margin
03/20/2007US7193923 Semiconductor memory device and access method and memory control system for same
03/20/2007US7193922 Semiconductor integrated circuit
03/20/2007US7193917 Semiconductor storage device, test method therefor, and test circuit therefor
03/20/2007US7193915 Semiconductor memory device
03/20/2007US7193910 Adjustable timing circuit of an integrated circuit
03/20/2007US7193903 Method of controlling an integrated circuit capable of simultaneously performing a data read operation and a data write operation
03/20/2007US7193449 Method and apparatus for generating multi-phase signal
03/15/2007WO2007030208A1 Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays
03/15/2007US20070061537 Processor system using synchronous dynamic memory
03/15/2007US20070058481 MRAM Internal Clock Pulse Generation with an ATD Circuit and the Method Thereof
03/15/2007US20070058480 NAND flash memory device with burst read latency function
03/15/2007US20070058479 Semiconductor integrated circuit device
03/15/2007US20070058478 Interface circuit
03/15/2007US20070058477 Accessing apparatus capable of reducing power consumption and accessing method thereof
03/15/2007US20070058476 Semiconductor memory device
03/15/2007US20070058475 Storage device employing a flash memory
03/15/2007US20070057696 Semiconductor integrated circuits with power reduction mechanism
03/15/2007DE102006033395A1 Integrated circuit component with erasable EEPROM memory, has first semiconductor-trough region of substrate which is split and electrically coupled by global control line by first and second byte-selection transistor
03/14/2007EP1761932A1 Dram with half and full density operation
03/14/2007EP1687827A4 Embedded memory with security row lock protection
03/14/2007CN1929026A Micro-tile memory interfaces
03/14/2007CN1305073C Word line decoding architecture in a flash memory
03/13/2007US7191380 Defect-tolerant and fault-tolerant circuit interconnections
03/13/2007US7191306 Flash memory, and flash memory access method and apparatus
03/13/2007US7191305 Method and apparatus for address decoding of embedded DRAM devices
03/13/2007US7190632 Semiconductor memory device having improved column selection lines and method of driving the same
03/13/2007US7190631 Multi-port memory
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