| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 05/30/2007 | CN1973337A Latched programming of memory and method |
| 05/30/2007 | CN1319169C Semiconductor integrated circuit having controllable internal power source and voltage |
| 05/29/2007 | US7225311 Method and apparatus for coordinating memory operations among diversely-located memory components |
| 05/29/2007 | US7225292 Memory module with termination component |
| 05/29/2007 | US7224639 Multi-phase clock signal generator and method having inherently unlimited frequency capability |
| 05/29/2007 | US7224638 Reliability clock domain crossing |
| 05/29/2007 | US7224637 Tri-mode clock generator to control memory array access |
| 05/29/2007 | US7224636 Semiconductor memory module |
| 05/29/2007 | US7224635 Fast read port for register file |
| 05/29/2007 | US7224634 Hardware security device for magnetic memory cells |
| 05/29/2007 | US7224632 Rewrite prevention in a variable resistance memory |
| 05/29/2007 | US7224631 Non-skipping auto-refresh in a DRAM |
| 05/29/2007 | US7224617 Nonvolatile semiconductor memory |
| 05/29/2007 | US7224596 Apparatus and method for repairing semiconductor memory device |
| 05/24/2007 | WO2007058617A1 A controller for non-volatile memories, and methods of operating the memory controller |
| 05/24/2007 | US20070118685 Block management for mass storage |
| 05/24/2007 | US20070118681 Data write-in method for flash memory |
| 05/24/2007 | US20070115752 Output Driver and Output Driving Method for Enhancing Initial Output Data Using Timing |
| 05/24/2007 | US20070115751 Latency control circuit and method thereof and an auto-precharge control circuit and method thereof |
| 05/24/2007 | US20070115750 Column decoder of semiconductor memory device, and method of generating column selection line signal in semiconductor memory device |
| 05/24/2007 | US20070115749 Voltage reference circuit using programmable metallization cells |
| 05/24/2007 | US20070115736 Semiconductor memory device having a single input terminal to select a buffer and method of testing the same |
| 05/24/2007 | DE10057489B4 Integrierter Speicher Built-in Memory |
| 05/23/2007 | EP1788578A1 Nonvolatile storage device and control method thereof |
| 05/23/2007 | EP1788575A1 Method for accessing in reading, writing and programming to a NAND non-volatile memory electronic device monolithically integrated on semiconductor |
| 05/23/2007 | CN1969337A Reconstruction of signal timing in integrated circuits |
| 05/23/2007 | CN1967719A Programmable logic device memory elements with elevated power supply levels |
| 05/23/2007 | CN1967713A High-capacity cache memory |
| 05/23/2007 | CN1317768C Nonvolatile memory device utilizing a vertical nanotube |
| 05/23/2007 | CN1317764C Semiconductor IC device and design method thereof |
| 05/23/2007 | CN1317643C Storage device, method for accessing storage device and Read-solomon decoder |
| 05/22/2007 | US7222214 Device-level address translation within a programmable non-volatile memory device |
| 05/22/2007 | US7221618 Semiconductor memory device having different synchronizing timings depending on the value of CAS latency |
| 05/22/2007 | US7221617 Backwards-compatible memory module |
| 05/22/2007 | US7221616 Word line driver circuits for use in semiconductor memory and driving method thereof |
| 05/22/2007 | US7221615 Semiconductor memory chip |
| 05/22/2007 | US7221613 Memory with serial input/output terminals for address and data and method therefor |
| 05/22/2007 | US7221612 SDRAM address mapping optimized for two-dimensional access |
| 05/22/2007 | US7221601 Timer lockout circuit for synchronous applications |
| 05/22/2007 | US7221593 Non-volatile memory device with erase address register |
| 05/22/2007 | US7221582 Method and system for controlling write current in magnetic memory |
| 05/22/2007 | US7221576 Dynamic RAM-and semiconductor device |
| 05/22/2007 | US7220652 Metal-insulator-metal capacitor and interconnecting structure |
| 05/17/2007 | US20070113117 Hybrid parallel/serial bus interface |
| 05/17/2007 | US20070111532 PAA-based etchant, methods of using same, and resultant structures |
| 05/17/2007 | US20070109909 Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent |
| 05/17/2007 | US20070109908 Individual Data Line Strobe-Offset Control in Memory Systems |
| 05/17/2007 | US20070109907 Synchronization circuit for a write operation on a semiconductor memory |
| 05/17/2007 | US20070109906 Word Line Driver For DRAM Embedded In A Logic Process |
| 05/17/2007 | US20070109905 Semiconductor memory device for achieving high reliability without increasing process complexity and cost |
| 05/17/2007 | US20070109904 Memory core and semiconductor memory device having the same |
| 05/17/2007 | US20070109903 Method of modeling physical layout of an electronic component in channel simulation |
| 05/17/2007 | US20070109859 Latched Programming of Memory and Method |
| 05/17/2007 | US20070109033 Memory Device Having a Duty Ratio Corrector |
| 05/17/2007 | US20070108482 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same |
| 05/16/2007 | CN1316737C Electric coupling machinery hand-pass filter |
| 05/15/2007 | US7219200 Method of accessing matrix data with address translation circuit that enables quick serial access in row or column directions |
| 05/15/2007 | US7218570 Apparatus and method for memory operations using address-dependent conditions |
| 05/15/2007 | US7218569 Memory circuit, and method for reading out data contained in the memory circuit using shared command signals |
| 05/15/2007 | US7218558 Semiconductor memory devices having column redundancy circuits therein that support multiple memory blocks |
| 05/15/2007 | US7218557 Method and apparatus for adaptive determination of timing signals on a high speed parallel bus |
| 05/10/2007 | WO2007053764A2 Crossbar-array designs and wire addressing methods that tolerate misalignment of electrical components at wire overlap points |
| 05/10/2007 | WO2007053335A2 Laser system |
| 05/10/2007 | WO2007053267A1 Memory array arranged in banks and sectorsand associated decoders |
| 05/10/2007 | US20070104018 Apparatus and method for improving dynamic refresh in a memory device |
| 05/10/2007 | US20070104017 Memory controller and memory system |
| 05/10/2007 | US20070104016 Semiconductor device and control method therefor |
| 05/10/2007 | US20070104015 Clock signal generation techniques for memories that do not generate a strobe |
| 05/10/2007 | US20070104014 Circuit arrangement for generating an n-bit output pointer, semiconductor memory and method for adjusting a read latency |
| 05/10/2007 | US20070104013 Apparatus for controlling column selecting signal of semiconductor memory apparatus and method of controlling the same |
| 05/10/2007 | US20070104012 Semiconductor storage device |
| 05/10/2007 | US20070104011 Cell array of semiconductor memory device and a method of forming the same |
| 05/10/2007 | US20070103995 Address decoding |
| 05/10/2007 | US20070103960 Method for operating a data storage apparatus employing passive matrix addressing |
| 05/10/2007 | DE102006049206A1 Leserverstärkerorganisation für Zwei-Zellen-Speicherbausteine Sense amplifier organization for two-cell memory modules |
| 05/10/2007 | DE102006047943A1 Arbeitszykluskorrekturvorrichtung Duty cycle corrector |
| 05/10/2007 | DE102005045311B4 Halbleiterspeicher, insbesondere Halbleiterspeicher mit Leseverstärker und Bitleitungs-Schalter A semiconductor memory, in particular semiconductor memory having sense amplifiers and bit line switch |
| 05/10/2007 | DE10138952B4 Halbleiterspeicherbauelement und Wortleitungsauswahlschaltung hierfür A semiconductor memory device, and word line selection circuit of this |
| 05/09/2007 | EP1782207A2 Method and system for optimizing the number of word line segments in a segmented mram array |
| 05/09/2007 | EP1200964B1 Method and apparatus for adjusting control signal timing in a memory device |
| 05/09/2007 | CN1961379A Method and apparatus for a dual power supply to embedded non-volatile memory |
| 05/09/2007 | CN1959841A Memory circuit |
| 05/08/2007 | US7215597 Memory device having components for transmitting and receiving signals synchronously |
| 05/08/2007 | US7215596 Circuit and method for controlling inversion of delay locked loop and delay locked loop and synchronous semiconductor memory device using the same |
| 05/08/2007 | US7215595 Memory device and method using a sense amplifier as a cache |
| 05/08/2007 | US7215594 Address latch circuit of memory device |
| 05/08/2007 | US7215592 Memory device with reduced word line resistance |
| 05/08/2007 | US7215591 Byte enable logic for memory |
| 05/08/2007 | US7215589 Semiconductor memory device that requires refresh operations |
| 05/08/2007 | US7215561 Semiconductor memory system having multiple system data buses |
| 05/08/2007 | US7215136 Semiconductor integrated circuits with power reduction mechanism |
| 05/03/2007 | US20070101224 Circuit for Generating Data Strobe Signal in DDR Memory Device, and Method Therefor |
| 05/03/2007 | US20070097781 DDR II write data capture calibration |
| 05/03/2007 | US20070097780 Performing read and write operations in the same cycle for an SRAM device |
| 05/03/2007 | US20070097779 Generating a sampling clock signal in a communication block of a memory device |
| 05/03/2007 | US20070097778 System and method for controlling timing of output signals |
| 05/03/2007 | US20070097777 Semiconductor device and method of manufacturing the same |
| 05/03/2007 | US20070097776 Memory control device and memory control method |
| 05/03/2007 | US20070097775 Flash memory device |
| 05/03/2007 | US20070097774 Semiconductor memory device |