| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 03/13/2007 | US7190630 Semiconductor storage device and method of selecting bit line of the semiconductor storage device |
| 03/13/2007 | US7190604 Capacity dividable memory IC |
| 03/13/2007 | US7190413 Memory video data storage structure optimized for small 2-D data transfer |
| 03/13/2007 | US7190203 Memory device having a duty ratio corrector |
| 03/08/2007 | US20070055812 Integrated circuit device mountable on both sides of a substrate and electronic apparatus |
| 03/07/2007 | CN1926634A 半导体存储器 Semiconductor memory |
| 03/07/2007 | CN1303661C Precharge apparatus in semiconductor memory device and precharge method using the same |
| 03/07/2007 | CN1303610C Method and appts. for synchronzation of row and column access operation |
| 03/06/2007 | US7187618 Circuit of SDRAM and method for data communication |
| 03/06/2007 | US7187617 Memory system and method for strobing data, command and address signals |
| 03/06/2007 | US7187616 MOS semiconductor integrated circuit device |
| 03/06/2007 | US7187615 Methods of selectively activating word line segments enabled by row addresses and semiconductor memory devices having partial activation commands of word line |
| 03/06/2007 | US7187614 Array read access control using MUX select signal gating of the read port |
| 03/06/2007 | US7187613 Method and apparatus for dynamically configuring redundant area of non-volatile memory |
| 03/06/2007 | US7187610 Flash/dynamic random access memory field programmable gate array |
| 03/06/2007 | US7187608 System and method for controlling the access and refresh of a memory |
| 03/06/2007 | US7187604 Semiconductor memory |
| 03/06/2007 | US7187597 Integrated circuit with circuitry for overriding a defective configuration memory cell |
| 03/06/2007 | US7187596 Semiconductor system having a source potential supply section |
| 03/06/2007 | US7187587 Programmable memory address and decode circuits with low tunnel barrier interpoly insulators |
| 03/06/2007 | US7187584 Method of reading multi-level NAND flash memory cell and circuit for the same |
| 03/06/2007 | US7187581 Semiconductor memory device and method of operating same |
| 03/06/2007 | US7187573 Memory circuit and method of generating the same |
| 03/01/2007 | WO2006017461A3 Byte enable logic for memory |
| 03/01/2007 | US20070047378 Method And Apparatus For Obtaining Memory Status Information Cross-Reference To Related Applications |
| 03/01/2007 | US20070047377 Printed circuit board for memory module, method of manufacturing the same and memory module/socket assembly |
| 03/01/2007 | US20070047376 Method and apparatus for synchronizing data from memory arrays |
| 03/01/2007 | US20070047375 Duty cycle detector with first and second oscillating signals |
| 03/01/2007 | US20070047374 Memory controller and memory system |
| 03/01/2007 | US20070047373 Storage device, control method of storage device, and control method of storage control device |
| 03/01/2007 | US20070047372 Semiconductor memory system and semiconductor memory chip |
| 03/01/2007 | US20070047371 Semiconductor transistor with multi-level transistor structure and method of fabricating the same |
| 03/01/2007 | US20070047370 Memory arrangement and method for addressing a memory arrangement |
| 03/01/2007 | US20070047369 Semiconductor device and control method of the same |
| 03/01/2007 | US20070047368 Semiconductor memory device having layered bit line structure |
| 03/01/2007 | US20070047367 Semiconductor memory devices, block select decoding circuits and method thereof |
| 03/01/2007 | US20070047366 Non-Volatile Memory Device |
| 03/01/2007 | US20070047342 Storage device and control method of storage device |
| 03/01/2007 | US20070047336 Semiconductor memory with wordline timing |
| 03/01/2007 | DE102006036837A1 Memory e.g. random access memory, managing method for use in e.g. file allocation system, file system, involves translating access unit address into storage unit address, where storage unit size is different as access unit size |
| 02/28/2007 | EP1758126A2 Nanoscale selection circuit |
| 02/28/2007 | EP1673782A4 Mram array with segmented word and bit lines |
| 02/28/2007 | CN1920879A Identifying and accessing individual memory devices in a memory channel |
| 02/27/2007 | US7185173 Column address path circuit and method for memory devices having a burst access mode |
| 02/27/2007 | US7184362 Page access circuit of semiconductor memory device |
| 02/27/2007 | US7184361 Method and apparatus for avoiding bi-directional signal fighting of serial interface |
| 02/27/2007 | US7184360 High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips |
| 02/27/2007 | US7184359 System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock |
| 02/27/2007 | US7184358 Semiconductor memory |
| 02/27/2007 | US7184357 Decoding circuit for memory device |
| 02/27/2007 | US7184356 Semiconductor memory device |
| 02/27/2007 | US7184355 Memory bank structure |
| 02/27/2007 | US7184353 Semiconductor device |
| 02/27/2007 | US7184346 Memory cell sensing with low noise generation |
| 02/27/2007 | US7184335 Electronic memory apparatus, and method for deactivating redundant bit lines or word lines |
| 02/27/2007 | US7184334 Semiconductor memory device and method of testing semiconductor memory device |
| 02/27/2007 | US7184326 Semiconductor memory |
| 02/27/2007 | US7184324 Semiconductor memory device having a single input terminal to select a buffer and method of testing the same |
| 02/27/2007 | US7184322 Semiconductor memory device and control method thereof |
| 02/27/2007 | US7184308 Flash memory devices and methods for programming the same |
| 02/27/2007 | US7184307 Flash memory device capable of preventing program disturbance according to partial programming |
| 02/27/2007 | US7184295 Memory device |
| 02/27/2007 | US7184289 Parallel electrode memory |
| 02/27/2007 | US7181966 Physical quantity sensor and method for manufacturing the same |
| 02/22/2007 | WO2007022368A2 Method and apparatus for synchronizing data between different clock domains in a memory controller |
| 02/22/2007 | US20070043922 Memory system for selectively transmitting command and address signals |
| 02/22/2007 | US20070041264 Method and apparatus for synchronizing data between different clock domains in a memory controller |
| 02/22/2007 | US20070041263 Row decoder circuit for electrically programmable and erasable non volatile memories |
| 02/22/2007 | US20070041262 Register file |
| 02/22/2007 | US20070041254 Synchronous semiconductor memory device for reducing power consumption |
| 02/22/2007 | DE102006032132A1 Schaltung und Verfahren zum Treiben einer Wortleitung eines Speicherbauelements Circuit and method for driving a word line of a memory device |
| 02/21/2007 | EP1754162A2 Method and device for managing a bus |
| 02/21/2007 | EP1623430A4 Semiconductor memory device and method of operating same |
| 02/21/2007 | CN1918662A Non-switching pre-and post-disturb compensational pulses |
| 02/21/2007 | CN1918660A Memory device with several random-access memory chip |
| 02/21/2007 | CN1918659A High voltage driver circuit with fast reading operation |
| 02/20/2007 | US7181643 Method for comparing the address of a memory access with an already known address of a faulty memory cell |
| 02/20/2007 | US7181591 Memory address decoding method and related apparatus by bit-pattern matching |
| 02/20/2007 | US7180824 Semiconductor memory device with a page mode |
| 02/20/2007 | US7180823 Flexible SDRAM clocking (MS-DLL) |
| 02/20/2007 | US7180822 Semiconductor memory device without decreasing performance thereof even if refresh operation or word line changing operation occur during burst operation |
| 02/20/2007 | US7180821 Memory device, memory controller and memory system having bidirectional clock lines |
| 02/20/2007 | US7180820 Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells |
| 02/20/2007 | US7180819 Converting dual port memory into 2 single port memories |
| 02/20/2007 | US7180818 High performance register file with bootstrapped storage supply and method of reading data therefrom |
| 02/20/2007 | US7180817 Semiconductor memory device with column selecting switches in hierarchical structure |
| 02/20/2007 | US7180816 Address coding method and address decoder for reducing sensing noise during refresh operation of memory device |
| 02/20/2007 | US7180808 Semiconductor memory device for performing refresh operation |
| 02/20/2007 | US7180794 Oscillating circuit, booster circuit, nonvolatile memory device, and semiconductor device |
| 02/20/2007 | US7180785 Nonvolatile semiconductor memory device with a plurality of sectors |
| 02/20/2007 | US7180768 Semiconductor memory device including 4TSRAMs |
| 02/20/2007 | US7180355 Level shifter circuit with stress test function |
| 02/20/2007 | US7180327 Memory module system with efficient control of on-die termination |
| 02/15/2007 | WO2007018661A2 Address decoding systems and methods |
| 02/15/2007 | WO2006116534A3 Nanoscale interconnection interface |
| 02/15/2007 | US20070036023 Method for detecting data strobe signal |
| 02/15/2007 | US20070036022 Synchronizer for multi-rate input data using unified first-in-first-out memory and method thereof |
| 02/15/2007 | US20070036021 Data reprogramming method and system |
| 02/15/2007 | US20070036020 Bit-deskewing IO method and system |
| 02/15/2007 | US20070036013 Semiconductor memory with wordline timing |