Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
12/2007
12/27/2007WO2007008325A3 Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations
12/27/2007US20070300015 Serial memory comprising means for protecting an extended memory array during a write operation
12/27/2007US20070297270 Semiconductor integrated circuit device
12/27/2007US20070297269 Memory and control unit
12/27/2007US20070297268 Random access memory including multiple state machines
12/27/2007US20070297267 Portable electronic device and coupling device for the same
12/27/2007US20070297266 Synchronous global controller for enhanced pipelining
12/27/2007US20070297265 Nonvolatile memory, apparatus and method for determining data validity of the same
12/27/2007US20070297264 Memory cell access circuit
12/27/2007US20070297260 Controlling execution of additional function during a refresh operation in a semiconductor memory device
12/27/2007US20070297259 Memory
12/27/2007US20070297257 Semiconductor memory device capable of canceling out noise development
12/27/2007US20070297255 Semiconductor memory tester
12/27/2007US20070297251 Semiconductor memory device having memory block configuration
12/27/2007US20070297250 Data processing apparatus and method using FIFO device
12/27/2007US20070297233 Nand flash memory and data programming method thereof
12/27/2007US20070297208 Semiconductor memory device
12/27/2007US20070296460 Semiconductor apparatus and signal processing system
12/27/2007US20070296019 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
12/27/2007DE102004023985B4 Verfahren zum Herstellen einer Wortleitung eines Speicherbausteins und Verwendung des Verfahrens zur Herstellung eines FIN-FET Transistors A method of manufacturing a word line of a memory chip and using the method of manufacturing a fin-FET transistor
12/26/2007EP1869679A2 Decoding circuit for non-binary groups of memory line drivers
12/26/2007CN100357912C Storage device
12/25/2007US7313768 Register file and method for designing a register file
12/25/2007US7313051 Output control signal generating circuit
12/25/2007US7313050 Word-line driver for memory devices
12/25/2007US7313049 Output circuit of a memory and method thereof
12/25/2007US7313044 Integrated semiconductor memory with temperature-dependent voltage generation
12/25/2007US7313023 Partition of non-volatile memory array to reduce bit line capacitance
12/25/2007US7312647 Memory device having a duty ratio corrector
12/25/2007US7312627 Decoding circuit for on die termination in semiconductor memory device and its method
12/21/2007WO2007122083B1 Dynamic memory cell structures
12/20/2007US20070291577 System with controller and memory
12/20/2007US20070291576 Address latch circuit of semiconductor memory device
12/20/2007US20070291575 Integrated Circuit Memory Devices That Support Selective Mode Register Set Commands and Related Methods
12/20/2007US20070291574 Method for manufacturing electro-optical device and electro-optical device
12/20/2007US20070291573 Semiconductor integrated circuit having data input/output circuit and method for inputting data using the same
12/20/2007US20070291572 Clock circuit for semiconductor memory
12/20/2007US20070291568 Apparatus and method for controlling refresh operation of semiconductor integrated circuit
12/20/2007US20070291557 Stacked semiconductor device
12/20/2007US20070291554 Memory with Clock-Controlled Memory Access and Method of Operating the Same
12/20/2007US20070291553 Data output circuits for an integrated circuit memory device in which data is output responsive to selective invocation of a plurality of clock signals, and methods of operating the same
12/20/2007US20070291550 Method and apparatus for high voltage operation for a high performance semiconductor memory device
12/20/2007US20070291528 Method and apparatus for improving SRAM cell stability by using boosted word lines
12/19/2007CN100356571C 半导体集成电路装置 The semiconductor integrated circuit device
12/19/2007CN100356479C Nonvolatile semiconductor storage equipment providing suitable programming voltage
12/18/2007US7310283 Apparatus and method for controlling clock signal in semiconductor memory device
12/18/2007US7310257 Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells
12/13/2007US20070286012 Method for controlling data output timing of memory device and device therefor
12/13/2007US20070286011 Memory device having data input and output ports and memory module and memory system including the same
12/13/2007US20070286010 Identical chips with different operations in a system
12/13/2007US20070286009 Serial memory interface
12/13/2007US20070286002 Method for writing to multiple banks of a memory device
12/13/2007US20070286000 Method and apparatus for synchronization of row and column access operations
12/13/2007US20070285989 Column decoding system for semiconductor memory devices implemented with low voltage transistors
12/12/2007EP1864094A1 Transistor layout configuration for tight-pitched memory array lines
12/12/2007EP1189139B1 Recording system, data recording device, memory device, and data recording method
12/12/2007CN100354971C Semiconductor method
12/11/2007US7307913 Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption
12/11/2007US7307912 Variable data width memory systems and methods
12/11/2007US7307900 Method and apparatus for optimizing strobe to clock relationship
12/11/2007US7307899 Reducing power consumption in integrated circuits
12/11/2007US7307891 Fast memory circuits and methods
12/11/2007US7307886 Nonvolatile memory device including circuit formed of thin film transistors
12/11/2007US7307865 Integrated read-only memory, method for operating said read-only memory and corresponding production method
12/06/2007WO2007140040A2 Contention-free hierarchical bit line in embedded memory and method thereof
12/06/2007WO2007018661A3 Address decoding systems and methods
12/06/2007US20070280034 System and method for performing low power dynamic trimming
12/06/2007US20070280033 Methods and devices for regulating the timing of control signals in integrated circuit memory devices
12/06/2007US20070280032 Built-in system and method for testing integrated circuit timing parameters
12/06/2007US20070280031 Nand type flash memory
12/06/2007US20070280030 Contention-free hierarchical bit line in embedded memory and method thereof
12/06/2007US20070280029 Connecting system between devices and connecting devices
12/06/2007US20070280028 Semiconductor device
12/06/2007US20070280027 Memory device and method having banks of different sizes
12/06/2007US20070280018 Semiconductor memory device, a local precharge circuit and method thereof
12/06/2007US20070279988 Apparatus and method for reduced peak power consumption during common operation of multi-NAND flash memory devices
12/05/2007CN101083131A Register file cell and circuits and methods for operating register file cell
12/05/2007CN100353454C A secure poly fuse rom with a power-on or on-reset hardware security features and method therefor
12/05/2007CN100353348C DRAM controller and DRAM control method
12/05/2007CN100353336C Data transmission method and system
12/04/2007US7304910 Semiconductor memory device with sub-amplifiers having a variable current source
12/04/2007US7304909 Control unit for deactivating and activating the control signals
12/04/2007US7304908 SRAM device capable of performing burst operation
12/04/2007US7304883 Semiconductor integrated circuit
12/04/2007US7304877 Semiconductor memory device with uniform data access time
11/2007
11/30/2007CA2586335A1 Mp3 playing with simplified user interactive generation and navigation of playlists
11/29/2007WO2007136944A2 Apparatus and method for reduced peak power consumption during common operation of multi-nand flash memory devices
11/29/2007WO2007136812A2 Memory array having row redundancy and method
11/29/2007WO2007115227A3 Multi-port memory device having variable port speeds
11/29/2007US20070274150 Non-volatile memory control
11/29/2007US20070274136 Semiconductor integrated circuit device
11/29/2007US20070274135 Low power and low timing jitter phase-lock loop and method
11/29/2007DE10227222B4 Halbleiterspeicherbauelement und Wortleitungsauswahlverfahren hierfür A semiconductor memory device, and word line selection method therefor
11/28/2007EP1614118A4 Low-voltage sense amplifier and method
11/27/2007US7301849 System for reducing row periphery power consumption in memory devices
11/27/2007US7301830 Semiconductor memory device and semiconductor device and semiconductor memory device control method
11/27/2007US7301824 Method and apparatus for communication within an integrated circuit
11/27/2007US7301802 Circuit arrays having cells with combinations of transistors and nanotube switching elements
11/27/2007US7301793 Semiconductor memory device
11/22/2007WO2007133849A2 Memory with level shifting word line driver and method thereof
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