Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
08/2007
08/23/2007US20070195635 Non-volatile memory device with page buffer having dual registers and methods using the same
08/23/2007US20070195634 Flat panel display device and fabrication apparatus thereof and fabrication method thereof
08/23/2007US20070195633 Multi-port semiconductor memory device and signal input/output method therefor
08/23/2007US20070195632 Semiconductor memory device having a global data bus
08/23/2007US20070195631 Control system for a dynamic random access memory and method of operation thereof
08/23/2007US20070195598 Accessing semiconductor memory device according to an address and additional access information
08/23/2007US20070195574 Semiconductor memory device and control method thereof
08/23/2007US20070195573 Dynamic ram-and semiconductor device
08/23/2007DE102007002192A1 Lokalwortleitungstreiberschema, um Ausfälle aufgrund einer schwebenden Wortleitung bei einem Segmentiert-Wortleitung-Treiberschema zu vermeiden Local word line driver scheme to avoid losses due to a floating word line in a segmented wordline driver scheme
08/22/2007EP1821312A1 Data transfer method and system including a volatile and a non-volatile memory
08/22/2007CN101023492A Semiconductor memory device with mos transistors each having floating gate and control gate
08/21/2007US7260020 Synchronous global controller for enhanced pipelining
08/21/2007US7260019 Memory array
08/21/2007US7260018 Multiport semiconductor memory device
08/21/2007US7260017 Non-volatile memory device having buffer memory with improve read speed
08/21/2007US7260016 Non-volatile semiconductor memory device and writing method therefor
08/21/2007US7260015 Memory device and method having multiple internal data buses and memory bank interleaving
08/21/2007US7260013 Power supply device in semiconductor memory
08/21/2007US7260001 Memory system having fast and slow data reading mechanisms
08/21/2007US7257954 Function switching method, function switching apparatus, data storage method, data storage apparatus, device, and air conditioner
08/16/2007US20070189106 Selectable clock unit
08/16/2007US20070189105 Flash memory device with rapid random access function and computing system including the same
08/16/2007US20070189104 Memory device with reduced word line resistance
08/16/2007US20070189103 Write latency tracking using a delay lock loop in a synchronous DRAM
08/16/2007US20070189102 Sram device with reduced leakage current
08/16/2007US20070189101 Fast read port for register file
08/16/2007US20070189100 Semiconductor memory
08/16/2007US20070189089 Method and Apparatus for Implementing High Speed Memory
08/16/2007US20070189084 Reduced pin count synchronous dynamic random access memory interface
08/16/2007US20070189054 Setting method of chip initial state
08/16/2007DE102006060803A1 Schreib-Burst-Stoppfunktion in einem leistungsarmen DDR-SDRAM Write burst stop function in a low-power DDR SDRAM
08/15/2007EP1819048A1 Semiconductor device employing dynamic circuit
08/14/2007US7257682 Synchronizing memory copy operations with memory accesses
08/14/2007US7257129 Memory architecture with multiple serial communications ports
08/14/2007US7257115 Data memory address generation for time-slot interchange switches
08/14/2007US7257047 Page buffer circuit of flash memory device with improved read operation function and method of controlling read operation thereof
08/14/2007US7257046 Memory data access scheme
08/14/2007US7257045 Uni-stage delay speculative address decoder
08/14/2007US7257039 Bit line discharge control method and circuit for a semiconductor memory
08/14/2007US7257034 Semiconductor integrated circuit device
08/14/2007US7257030 Operating a storage component
08/14/2007US7257020 Thin film magnetic memory device having redundant configuration
08/14/2007US7256790 Video and graphics system with MPEG specific data transfer commands
08/09/2007US20070186030 Fast random access DRAM management method
08/09/2007US20070183251 Simplified power-down mode control circuit utilizing active mode operation control signals
08/09/2007US20070183250 High speed, low power, low leakage read only memory
08/09/2007US20070183249 Command decoder circuit of semiconductor memory device
08/09/2007US20070183247 Semiconductor device
08/09/2007US20070183239 Semiconductor memory device including plurality of memory mats
08/09/2007US20070183213 Nonvolatile semiconductor memory device
08/09/2007US20070183211 Semiconductor device and method of controlling the same
08/08/2007EP1816570A2 Integrated circuit I/O using a high performance bus interface
08/08/2007EP1816569A2 Integrated circuit I/O using a high performance bus interface
08/08/2007CN101015019A Apparatus and method for selectively configuring a memory device using a bi-stable relay
08/07/2007US7254758 Method and apparatus for testing circuit units to be tested with different test mode data sets
08/07/2007US7254090 Semiconductor memory device
08/07/2007US7254089 Memory with selectable single cell or twin cell configuration
08/07/2007US7254088 Semiconductor memory
08/07/2007US7254087 Multi-port memory device
08/07/2007US7254086 Method for accessing memory
08/07/2007US7254082 Semiconductor device
08/07/2007US7254069 Semiconductor memory device storing redundant replacement information with small occupation area
08/07/2007US7254062 Circuit for selecting/deselecting a bitline of a non-volatile memory
08/07/2007US7254060 Nonvolatile semiconductor memory device
08/07/2007US7254055 Initial firing method and phase change memory device for performing firing effectively
08/07/2007US7253387 List mode multichannel analyzer
08/02/2007WO2007085893A1 Method for utilizing a memory interface to control partitioning of a memory module
08/02/2007US20070177449 Semiconductor memory, memory controller and control method for semiconductor memory
08/02/2007US20070177448 Access port for use in electrochemical cells
08/02/2007US20070177447 Memory Having a Layer with Electrical Conductivity Anisotropy
08/02/2007US20070177446 System and method for application configuration for performance test
08/02/2007US20070177445 Semiconductor device
08/02/2007DE10102351B4 Integrierter Speicher Built-in Memory
08/01/2007EP1410399A4 Method and apparatus for decreasing block write operation times performed on nonvolatile memory
08/01/2007CN1329917C Magnetic storage device
07/2007
07/31/2007US7251194 Memory system and method for strobing data, command and address signals
07/31/2007US7251193 Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent
07/31/2007US7251192 Register read for volatile memory
07/31/2007US7251191 Method for controlling time point for data output in synchronous memory device
07/31/2007US7251190 Non-volatile semiconductor memory device
07/31/2007US7251189 Semiconductor storage device
07/31/2007US7251187 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
07/31/2007US7251185 Methods and apparatus for using memory
07/31/2007US7251184 Semiconductor memory device
07/31/2007US7251182 Semiconductor memory device and semiconductor integrated circuit device
07/31/2007US7251176 Semiconductor memory device
07/31/2007US7251175 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
07/31/2007US7251172 Efficient register for additive latency in DDR2 mode of operation
07/31/2007US7251171 Semiconductor memory and system apparatus
07/31/2007US7251155 Device and method having a memory array storing each bit in multiple memory cells
07/26/2007WO2007053764A3 Crossbar-array designs and wire addressing methods that tolerate misalignment of electrical components at wire overlap points
07/26/2007US20070171763 Circuit and method for controlling write recovery time in semiconductor memory device
07/26/2007US20070171762 Method and Apparatus to Control Sensing Time for Nonvolatile Memory
07/26/2007US20070171761 Methods and Tangible Objects Employing Machine Readable Data
07/26/2007US20070171760 Apparatus and method for trimming static delay of a synchronizing circuit
07/26/2007US20070171759 Semiconductor memory device, system and method of testing same
07/26/2007US20070171758 Semiconductor memory device adapted to communicate decoding signals in a word line direction
07/26/2007US20070171757 System and method of selective row energization based on write data
07/26/2007US20070171756 Double byte select high voltage line for EEPROM memory block
07/26/2007US20070171755 Semiconductor memory device and method therefor
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