| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
|---|
| 07/29/1998 | CN1188934A 半导体电路 Semiconductor circuit |
| 07/28/1998 | US5787498 Integrated circuit memory with verification unit which resets an address translation register upon failure to define one-to-one correspondences between addresses and memory cells |
| 07/28/1998 | US5787454 Recorder buffer with interleaving mechanism for accessing a multi-parted circular memory array |
| 07/28/1998 | US5787047 Memory architecture for burst mode access |
| 07/28/1998 | US5787045 Internal address generator of semiconductor memory device |
| 07/22/1998 | EP0853806A1 Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell |
| 07/21/1998 | US5784330 Evenly distributed RC delay word line decoding and mapping |
| 07/21/1998 | US5784311 Two-device memory cell on SOI for merged logic and memory applications |
| 07/21/1998 | US5783962 Bootstrap circuit and integrated memory circuit having the bootstrap circuit |
| 07/21/1998 | US5783949 Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories |
| 07/14/1998 | US5781627 Semiconductor integrated circuit device with copy-preventive function |
| 07/14/1998 | US5781498 Sub word line driving circuit and a semiconductor memory device using the same |
| 07/14/1998 | US5781497 Random access memory word line select circuit having rapid dynamic deselect |
| 07/14/1998 | US5781493 Semiconductor memory device having block write function |
| 07/14/1998 | US5781483 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array |
| 07/14/1998 | US5781481 Semiconductor memory device with reduced leakage current and improved data retention |
| 07/14/1998 | US5781480 Pipelined dual port integrated circuit memory |
| 07/14/1998 | US5781472 Write path circuit for writing data |
| 07/14/1998 | US5781200 Tile memory mapping for increased throughput in a dual bank access DRAM |
| 07/14/1998 | US5781037 Method and apparatus for an address transition detection circuit |
| 07/08/1998 | EP0852380A2 Variable latency memory circuit |
| 07/08/1998 | EP0852032A1 Single chip microprocessor, math co-processor, random number generator, real-time clock and ram having a one-wire interface |
| 07/07/1998 | US5778425 Electronic system having a first level write through cache memory and smaller second-level write-back cache memory and method of operating the same |
| 07/07/1998 | US5778243 In a multi-threaded computer system |
| 07/07/1998 | US5777946 Semiconductor memory circuit equipped with a column addressing circuit having a shift register |
| 07/07/1998 | US5777945 Column decoding circuit for semiconductor memory device |
| 07/07/1998 | US5777943 Column decoder for a semiconductor memory device |
| 07/07/1998 | US5777929 Multiport memory cell circuit having read buffer for reducing read access time |
| 07/07/1998 | US5777928 Apparatus for storing data |
| 07/07/1998 | US5777923 Flash memory read/write controller |
| 07/07/1998 | US5777492 Address transition detector circuit |
| 07/02/1998 | WO1998028749A1 Non-volatile memory array that enables simultaneous read and write operations |
| 07/02/1998 | WO1998028747A1 Memory and method for sensing sub-groups of memory elements |
| 07/01/1998 | EP0851426A2 Memory block for realizing semiconductor memory devices and corresponding manufacturing process |
| 07/01/1998 | EP0850481A1 Device for skip addressing certain lines in a serially operating digital store |
| 07/01/1998 | EP0850480A1 Fast word line decoder for memory devices |
| 07/01/1998 | EP0850440A1 Secure module with microprocessor and co-processor |
| 07/01/1998 | EP0771463B1 Process and device for storing and rotating bit configurations |
| 06/30/1998 | US5774413 Sensed wordline driver |
| 06/30/1998 | US5774412 Local word line phase driver |
| 06/30/1998 | US5774410 Semiconductor storage device |
| 06/30/1998 | US5774409 Multi-bank dRAM suitable for integration with processor on common semiconductor chip |
| 06/30/1998 | US5774407 Dram bit line selection circuit for selecting multiple pairs of lines |
| 06/30/1998 | US5774402 Initialization circuit for a semiconductor memory device |
| 06/30/1998 | US5774396 Flash memory with row redundancy |
| 06/30/1998 | US5773892 Multi-port semiconductor memory device with reduced coupling noise |
| 06/24/1998 | EP0849740A1 Method and reading device with memory prediction |
| 06/24/1998 | EP0849739A1 Device and method for incremental reading of a memory |
| 06/24/1998 | EP0849737A2 Improvements in or relating to electronic systems |
| 06/24/1998 | EP0848851A1 Segmented read line circuit particularly useful for multi-port storage arrays |
| 06/24/1998 | CN1185856A Process for the selective programming of a non-volatile store |
| 06/23/1998 | US5771369 Memory row redrive |
| 06/23/1998 | US5771199 Integrated circuit memory devices having improved dual memory bank control capability and methods of operating same |
| 06/18/1998 | WO1998026423A1 Bi-directional shift register |
| 06/17/1998 | EP0848484A2 Circuit for generating a boosted output voltage |
| 06/16/1998 | US5768214 Semiconductor memory device |
| 06/16/1998 | US5768211 Multi-port arbitration for high performance width expansion |
| 06/16/1998 | US5768209 Semiconductor memory with NAND type memory cells having NOR gate operation delay means |
| 06/16/1998 | US5768205 Process of transfering streams of data to and from a random access memory device |
| 06/16/1998 | US5768199 Semiconductor memory device with dual precharge operations |
| 06/16/1998 | US5768196 Shift-register based row select circuit with redundancy for a FIFO memory |
| 06/16/1998 | US5768193 Bit-refreshable method and circuit for refreshing a nonvolatile flash memory |
| 06/16/1998 | US5768173 Memory modules, circuit substrates and methods of fabrication therefor using partially defective memory devices |
| 06/11/1998 | WO1998025345A1 Clock vernier adjustment |
| 06/10/1998 | EP0847058A2 Improvements in or relating to integrated circuits |
| 06/10/1998 | EP0782746B1 Storage device and process for simultaneously reading and recording data |
| 06/09/1998 | US5765219 Apparatus and method for incrementally accessing a system memory |
| 06/09/1998 | US5765212 Memory control circuit that selectively performs address translation based on the value of a road start address |
| 06/09/1998 | US5764591 Memory device and memory control circuit |
| 06/09/1998 | US5764589 Array row and column decoder apparatus and method |
| 06/09/1998 | US5764588 Memory circuit |
| 06/09/1998 | US5764587 Static wordline redundancy memory device |
| 06/09/1998 | US5764585 Semiconductor memory device having main word lines and sub word lines |
| 06/09/1998 | US5764583 In a two-dimensional array |
| 06/03/1998 | EP0845784A1 Method and corresponding circuit for generating a syncronization ATD signal |
| 06/02/1998 | US5761697 Identifiable modules on a serial bus system and corresponding identification methods |
| 06/02/1998 | US5761694 Multi-bank memory system and method having addresses switched between the row and column decoders in different banks |
| 06/02/1998 | US5761472 Interleaving block operations employing an instruction set capable of delaying block-store instructions related to outstanding block-load instructions in a computer system |
| 06/02/1998 | US5761181 Method of fabricating an electro-optical memory |
| 06/02/1998 | US5761151 Pulse generator for generating a plurality of output pulses in response to an input pulse |
| 06/02/1998 | US5761150 Synchronous memory with pipelined write operation |
| 06/02/1998 | US5761149 Dynamic RAM |
| 06/02/1998 | US5761148 For an integrated circuit |
| 06/02/1998 | US5761147 Virtual two-port memory structure with fast write-thru operation |
| 06/02/1998 | US5761136 Circuit for generating a column switch enable signal of a memory |
| 06/02/1998 | US5761135 Sub-word line drivers for integrated circuit memory devices and related methods |
| 06/02/1998 | US5760608 High speed, low clock load register dump circuit |
| 06/02/1998 | US5760607 System comprising field programmable gate array and intelligent memory |
| 05/28/1998 | WO1998023032A1 An address transition detection circuit |
| 05/28/1998 | WO1998022950A1 Write protected, non-volatile memory device with user programmable sector lock capability |
| 05/27/1998 | EP0844617A2 Improvements in or relating to electronic circuits |
| 05/27/1998 | CN1183164A Method and apparatus for reducing latency time on an interface by overlapping transmitted packets |
| 05/27/1998 | CN1183163A Nonvolatile memory blocking architecture |
| 05/27/1998 | CN1183162A Nonvolatile memory blocking architecture and redundancy |
| 05/26/1998 | US5757718 Semiconductor memory device having address transition detection circuit for controlling sense and latch operations |
| 05/26/1998 | US5757717 Semiconductor circuit having circuit supplying voltage higher than power supply voltage |
| 05/26/1998 | US5757704 Semiconductor memory integrated circuit with simplified circuit structure |
| 05/26/1998 | US5757698 Nonvolatile semiconductor for reading data at a read request even during the writing of data |
| 05/26/1998 | US5757689 Semiconductor memory activated by plurality of word lines on same row |
| 05/20/1998 | EP0843316A2 Non-volatile semiconductor memory device |