| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
|---|
| 09/29/1998 | US5815458 System and method for writing data to memory cells so as to enable faster reads of the data using dual wordline drivers |
| 09/29/1998 | US5815457 Bit line selection decoder for an electronic memory |
| 09/29/1998 | US5815453 Semiconductor memory device having redundant decoder with subtantially constant margin regardless of power voltage level |
| 09/29/1998 | US5815448 Semiconductor memory having redundancy circuit |
| 09/29/1998 | US5815443 Memory cell |
| 09/29/1998 | US5815440 Semiconductor memory device with electrically controllable threshold voltage |
| 09/29/1998 | US5815432 Single-ended read, dual-ended write SCRAM cell |
| 09/29/1998 | US5815425 Combined digital write and analog rewrite process for non-volatile memory |
| 09/24/1998 | DE19800344A1 Double word line decoder circuit for DRAM memory cells |
| 09/23/1998 | EP0866616A1 Method of and apparatus for transmitting data |
| 09/23/1998 | EP0866613A1 Preventing fraudulent access in a conditional access system |
| 09/23/1998 | EP0866611A1 Broadcast receiving system comprising a computer and a decoder |
| 09/22/1998 | US5812486 Dual port ram |
| 09/22/1998 | US5812485 Synchronous graphic RAM having block write control function |
| 09/22/1998 | US5812483 Integrated circuit memory devices including split word lines and predecoders and related methods |
| 09/22/1998 | US5812482 Wordline wakeup circuit for use in a pulsed wordline design |
| 09/22/1998 | US5812479 Programmable logic array integrated circuits |
| 09/22/1998 | US5812469 Method and apparatus for testing multi-port memory |
| 09/22/1998 | US5812461 Driver circuit for addressing core memory and a method for the same |
| 09/22/1998 | US5812459 Nonvolatile semiconductor memory device having row decoder supplying a negative potential to wordlines during erase mode |
| 09/22/1998 | US5812446 For storing sensitive information elements |
| 09/17/1998 | WO1998040892A1 Pump control circuit |
| 09/17/1998 | WO1998040891A1 Dram with integral sram and systems and methods using the same |
| 09/16/1998 | EP0865042A2 Drive circuit, and semiconductor memory device that utilizes same |
| 09/15/1998 | US5809565 Method of and device for writing and reading data items in a memory system including a data item memory and a length memory |
| 09/15/1998 | US5809553 Nonvolatile memory devices including lockable word line cells |
| 09/15/1998 | US5809549 Method of retrieving data from a synchronous memory device |
| 09/15/1998 | US5809519 Systems and methods to convert signals multiplexed on a single wire to three wire |
| 09/15/1998 | US5809518 Command/data transfer protocol for one-wire-bus architecture |
| 09/15/1998 | US5809263 Integrated circuit I/O using a high performance bus interface |
| 09/15/1998 | US5808957 Address buffers of semiconductor memory device |
| 09/15/1998 | US5808955 Integrated circuit memory devices including sub-word line drivers and related methods |
| 09/15/1998 | US5808954 Semiconductor memory device having stabilizing circuit of word line activating voltage |
| 09/15/1998 | US5808500 Block architecture semiconductor memory array utilizing non-inverting pass gate local wordline driver |
| 09/15/1998 | US5808482 For a semiconductor device |
| 09/11/1998 | WO1998039773A1 Non-volatile memory enabling simultaneous reading and writing by time multiplexing a decode path |
| 09/09/1998 | EP0863512A1 Dual-port memory |
| 09/08/1998 | US5806082 Wrap-around mechanism for memory split-wordline read |
| 09/08/1998 | US5806070 Device and method for controlling solid-state memory system |
| 09/08/1998 | US5805854 System and process for memory column address organization in a computer system |
| 09/08/1998 | US5805521 DRAM memory system |
| 09/08/1998 | US5805520 Integrated circuit address reconfigurability |
| 09/08/1998 | US5805519 Semiconductor memory device |
| 09/08/1998 | US5805518 Memory circuit accommodating both serial and random access, having a synchronous DRAM device for writing and reading data |
| 09/08/1998 | US5805517 Self-calibrating address transition detection scheme |
| 09/08/1998 | US5805510 Data erase mechanism for nonvolatile memory of boot block type |
| 09/08/1998 | US5805509 Method and structure for generating a boosted word line voltage and back bias voltage for a memory array |
| 09/08/1998 | US5805506 Semiconductor device having a latch circuit for latching data externally input |
| 09/08/1998 | US5805476 Very large scale integrated circuit for performing bit-serial matrix transposition operation |
| 09/08/1998 | US5804989 Logic circuit for a semiconductor memory device |
| 09/03/1998 | WO1998038646A1 High voltage nmos pass gate for flash memory with high voltage generator |
| 09/02/1998 | EP0862184A2 Semiconductor storage device capable of accurately collectively executing erase verify operation on all memory cells |
| 09/02/1998 | EP0862183A1 Voltage level shifter device, particularly for a non-volatile memory |
| 09/02/1998 | EP0862181A2 Static type semiconductor memory device with timer circuit |
| 09/02/1998 | CN1192029A Static type semiconductor memory device with timer circuit |
| 09/01/1998 | US5802583 Sysyem and method providing selective write protection for individual blocks of memory in a non-volatile memory device |
| 09/01/1998 | US5802579 System and method for simultaneously reading and writing data in a random access memory |
| 09/01/1998 | US5802555 Computer system including a refresh controller circuit having a row address strobe multiplexer and associated method |
| 09/01/1998 | US5802540 Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices |
| 09/01/1998 | US5802008 Word line driver in semiconductor memory device using a main decoder and a plurality of middle and sub-decoders |
| 09/01/1998 | US5802006 Semiconductor memory of multiple-bank structure having block write function |
| 09/01/1998 | US5802003 System for implementing write, initialization, and reset in a memory array using a single cell write port |
| 09/01/1998 | US5802001 Burn-in checking apparatus for semiconductor memory device |
| 09/01/1998 | US5801991 Deselected word line that floats during MLC programming of a flash memory |
| 09/01/1998 | US5801981 Serial access memory with reduced loop-line delay |
| 09/01/1998 | US5801980 Testing of an analog memory using an on-chip digital input/output interface |
| 09/01/1998 | US5801579 High voltage NMOS pass gate for integrated circuit with high voltage generator |
| 09/01/1998 | US5801576 Semiconductor integrated circuit device having a hierarchical power source configuration |
| 08/27/1998 | DE19749659A1 Hierarchical word conductor structure for semiconductor memory device |
| 08/25/1998 | US5798979 Clock-synchronous semiconductor memory device and access method thereof |
| 08/25/1998 | US5798978 Semiconductor memory device with multibank structure |
| 08/20/1998 | WO1998036419A1 Semiconductor integrated circuit device |
| 08/19/1998 | EP0763240A4 Bit map addressing schemes for flash memory |
| 08/18/1998 | US5796675 To transmit input data to an internal circuit |
| 08/18/1998 | US5796674 Signal transition detection circuit |
| 08/18/1998 | US5796667 Bit map addressing schemes for flash memory |
| 08/18/1998 | US5796664 Semiconductor memory device having divided word line |
| 08/18/1998 | US5796657 Flash memory with flexible erasing size from multi-byte to multi-block |
| 08/18/1998 | US5796651 Memory device using a reduced word line voltage during read operations and a method of accessing such a memory device |
| 08/18/1998 | US5796293 Voltage boosting circuits having backup voltage boosting capability |
| 08/12/1998 | EP0645713B1 Word line redundancy nonvolatile semiconductor memory |
| 08/11/1998 | US5793699 Circuit for the generation and reset of timing signal used for reading a memory device |
| 08/11/1998 | US5793698 Semiconductor read-only VLSI memory |
| 08/11/1998 | US5793695 Semiconductor memory device having level-shifted precharge signal |
| 08/11/1998 | US5793681 Multiport memory cell circuit having read buffer for reducing read access time |
| 08/11/1998 | US5793676 Nonvolatile memory device having sectors of selectable size and number |
| 08/11/1998 | US5793669 High density two port memory cell |
| 08/11/1998 | US5793383 Method of displaying video information stored in a video memory |
| 08/11/1998 | US5793317 Low power approach to state sequencing and sequential memory addressing in electronic systems |
| 08/11/1998 | US5792682 Method for reducing charge loss |
| 08/05/1998 | CN1189902A Semiconductor memory having arithmetic function, and processor using the same |
| 08/05/1998 | CN1189672A Circuit arrangement for generating increased output voltage |
| 08/04/1998 | US5790883 Multiple ports storage device with programmable overlapped data bits access |
| 08/04/1998 | US5790470 Decoder circuit having a predecoder acitivated by a reset signal |
| 08/04/1998 | US5790464 Method for arranging a memory cell array in semiconductor memory device |
| 08/04/1998 | US5790461 Register file with bypass capability |
| 08/04/1998 | US5789938 Structure and method for reading blocks of data from selectable points in a memory device |
| 07/30/1998 | WO1998033182A1 Data routing devices |
| 07/30/1998 | WO1998032344A1 CALCIUM FORTIFIED LOW pH BEVERAGE |
| 07/29/1998 | EP0855650A1 Structure to recover a portion of a partially functional embedded memory |