| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 07/21/2004 | CN1158663C Dram |
| 07/20/2004 | US6765845 Hierarchical word line scheme with decoded block selecting signals and layout method of the same |
| 07/20/2004 | US6765844 Semiconductor memory device having a hierarchical I/O structure |
| 07/20/2004 | US6765843 Semiconductor memory device with efficient buffer control for data buses |
| 07/20/2004 | US6765842 Hole driver in semiconductor memory device |
| 07/20/2004 | US6765841 Semiconductor memory device and electronic instrument |
| 07/20/2004 | US6765836 Semiconductor memory with a clock synchronization device having a temperature controlled delay circuit |
| 07/20/2004 | US6765815 Semiconductor memory device having a main word-line layer disposed above a column selection line layer |
| 07/20/2004 | US6765814 Semiconductor memory device |
| 07/15/2004 | US20040139472 Transmission and reception of television programmes and other data |
| 07/15/2004 | US20040139271 Multi-ported register files |
| 07/15/2004 | US20040136259 Memory structure, a system, and an electronic device, as well as a method in connection with a memory circuit |
| 07/15/2004 | US20040136258 Semiconductor memory device and mount-type semiconductor device |
| 07/15/2004 | US20040136242 Voltage boost device and memory system |
| 07/15/2004 | US20040136222 Programmable mask ROM building element and process of manufacture |
| 07/15/2004 | US20040136218 Memory device composed of a plurality of memory chips in a single package |
| 07/15/2004 | US20040135605 Delay locked loops having delay time compensation and methods for compensating for delay time of the delay locked loops |
| 07/15/2004 | US20040135604 Delay locked loops having blocking circuits therein that enhance phase jitter immunity and methods of operating same |
| 07/15/2004 | DE10358356A1 Schaltung zur Kompensation der Einschalt- und Ausschaltspannung einer Wortleitung auf der Basis der Schwellenspannung eines Feldelementes A circuit for compensation of the switch-on and turn-off of a word line based on the threshold voltage of a field element |
| 07/15/2004 | DE10335070A1 Halbleiterspeichervorrichtung mit einer Speicherzelle mit geringem Zellverhältnis A semiconductor memory device having a memory cell with a small cell ratio |
| 07/14/2004 | EP1437660A2 Semiconductor memory device and mount-type semiconductor device |
| 07/14/2004 | CN1512508A Method for driving word line using word line driver |
| 07/13/2004 | US6763480 Flash EEprom system |
| 07/13/2004 | US6763026 Memory used in packet switching network for successively storing data bits in data storage region and serially outputting data bits and method used therein |
| 07/13/2004 | US6762974 Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM |
| 07/13/2004 | US6762971 Semiconductor memory device |
| 07/13/2004 | US6762959 Low-power nonvolatile semiconductor memory device |
| 07/13/2004 | US6762958 Semiconductor memory with precharge control |
| 07/13/2004 | US6762952 Minimizing errors in a magnetoresistive solid-state storage device |
| 07/13/2004 | US6762949 Dynamic RAM-and semiconductor device |
| 07/13/2004 | US6762474 Method and apparatus for temperature compensation of read-only memory |
| 07/08/2004 | WO2004029980A3 Refresh control circuit for ics with a memory array |
| 07/08/2004 | US20040133730 Fast random access DRAM management method |
| 07/08/2004 | US20040130963 Program counting circuit and program word line voltage generating circuit in flash memory device using the same |
| 07/08/2004 | US20040130949 String programmable nonvolatile memory with NOR architecture |
| 07/08/2004 | US20040130948 String programmable nonvolatile memory with NOR architecture |
| 07/08/2004 | US20040130931 Semiconductor memory device with memory cell having low cell ratio |
| 07/08/2004 | US20040130363 Storing an unchanging binary code in an integrated circuit |
| 07/08/2004 | US20040129974 System with meshed power and signal buses on cell array |
| 07/08/2004 | US20040129952 Integrated circuit with programmable fuse array |
| 07/08/2004 | DE19618781B4 Halbleiterspeichervorrichtung mit hierarchischer Spaltenauswahlleitungsstruktur A semiconductor memory device having a hierarchical column select line structure |
| 07/08/2004 | DE19604764B4 Halbleiterspeichereinrichtung und Verfahren zum Auswählen einer Wortleitung in einer Halbleiterspeichereinrichtung A semiconductor memory device and method for selecting a word line in a semiconductor memory device |
| 07/08/2004 | DE10256509A1 Verfahren zum Adressieren von blockweise löschbaren Speichern Method of addressing block-erasable memories |
| 07/08/2004 | DE10239322B4 Integrierter Speicher und Verfahren zur Einstellung der Latenzzeit im integrierten Speicher Integrated memory and method for adjusting the latency integrated memory |
| 07/07/2004 | EP1435098A2 Mram bit line word line architecture |
| 07/06/2004 | US6760273 Buffer using two-port memory |
| 07/06/2004 | US6760271 Semiconductor memory device with shorter signal lines |
| 07/06/2004 | US6760243 Distributed, highly configurable modular predecoding |
| 07/06/2004 | US6759884 Semiconductor integrated circuit, method of controlling the same, and variable delay circuit |
| 07/06/2004 | US6759871 Line segmentation in programmable logic devices having redundancy circuitry |
| 07/06/2004 | US6759870 Programmable logic array integrated circuits |
| 07/01/2004 | WO2004055822A2 Tamper-resisting packaging |
| 07/01/2004 | US20040128429 Method of addressing individual memory devices on a memory module |
| 07/01/2004 | US20040125930 Identification of an integrated circuit from its physical manufacture parameters |
| 07/01/2004 | US20040125686 Address counter strobe test mode device |
| 07/01/2004 | US20040125685 Pointer generator for stack |
| 07/01/2004 | US20040125684 Semiconductor memory device and address conversion circuit |
| 07/01/2004 | US20040125683 Semiconductor integrated circuit device |
| 07/01/2004 | US20040125650 Magnetic random access memory device with a reduced number of interconnections for selection of address |
| 07/01/2004 | US20040125640 Synchronous semiconductor memory device having clock synchronization circuit and circuit for controlling on/off of clock tree of the clock synchronization circuit |
| 07/01/2004 | US20040125636 Interleaved wordline architecture |
| 07/01/2004 | US20040124896 Delay locked loop capable of compensating for delay of internal clock signal by variation of driving strength of output driver in semiconductor memory device |
| 07/01/2004 | US20040124510 On die voltage regulator |
| 06/30/2004 | EP1434238A2 Integrated circuit with programmable fuse array |
| 06/30/2004 | EP1153393A4 Improved word line boost circuit |
| 06/30/2004 | CN1509475A Memory cell circuit, memory device, motion vector detection device and motion compensation prediction coding device |
| 06/30/2004 | CN1508806A Semiconductor stroage device with storage unit of low unit ratio |
| 06/30/2004 | CN1508706A Compound storage device |
| 06/30/2004 | CN1508693A High-speed programmable non-volatile semiconductor storage device |
| 06/29/2004 | US6757842 Flash EEprom system |
| 06/29/2004 | US6757806 Method for converting addresses in a semiconductor memory device and apparatus therefor |
| 06/29/2004 | US6757799 Memory device with pipelined address path |
| 06/29/2004 | US6757779 Content addressable memory with selectable mask write mode |
| 06/29/2004 | US6756813 Voltage translator |
| 06/29/2004 | US6756652 Semiconductor memory device with efficiently laid-out internal interconnection lines |
| 06/27/2004 | CA2453695A1 Semiconductor memory device and mount-type semiconductor device |
| 06/24/2004 | US20040120212 Data transfer system capable of transferring data at high transfer speed |
| 06/24/2004 | US20040120211 Interleaved delay line for phase locked and delay locked loops |
| 06/24/2004 | US20040120210 Semiconductor memory devices with delayed auto-precharge function and associated methods of auto-precharging semiconductor memory devices |
| 06/24/2004 | US20040120209 Semiconductor memory device supporting two data ports |
| 06/24/2004 | US20040120208 Memory having multiple write ports and write insert unit, and method of operation |
| 06/24/2004 | US20040120207 Memory having multiple write ports and method of operation |
| 06/24/2004 | US20040120206 Composite memory device |
| 06/24/2004 | US20040120199 Reduced read delay for single-ended sensing |
| 06/24/2004 | US20040120197 Memory cell circuit, memory device, motion vector detection device, and motion compensation prediction coding device |
| 06/24/2004 | US20040119515 Register controlled delay locked loop |
| 06/24/2004 | US20040119512 Interleaved delay line for phase locked and delay locked loops |
| 06/24/2004 | DE69333373T2 Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften A non-volatile semiconductor memory having electrically and collectively erasable characteristics |
| 06/23/2004 | EP1431678A1 Function switching method, function switching apparatus, data storage method, data storage apparatus, device, and air conditioner |
| 06/23/2004 | CN1507631A Method and apparatus for biasing selected and unselected array lines when writing a memory array |
| 06/23/2004 | CN1507060A 半导体存储装置 The semiconductor memory device |
| 06/23/2004 | CN1506970A Selection of memory unit in data storing apparatus |
| 06/23/2004 | CN1155004C Semiconductor memory device |
| 06/22/2004 | US6754797 Address converter apparatus and method to support various kinds of memory chips and application system thereof |
| 06/22/2004 | US6754131 Word line driver for negative voltage |
| 06/22/2004 | US6754130 Memory having multiple write ports and write insert unit, and method of operation |
| 06/22/2004 | US6754126 Semiconductor memory |
| 06/22/2004 | US6754118 Method for writing to multiple banks of a memory device |
| 06/22/2004 | US6754114 Semiconductor device having redundancy circuit |
| 06/22/2004 | US6754111 Dual bandgap voltage reference system and method for reducing current consumption during a standby mode of operation and for providing reference stability during an active mode of operation |