| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 05/20/2004 | US20040095817 Pattern layout of transfer transistors employed in row decoder |
| 05/20/2004 | US20040095802 Selection of memory cells in data storage devices |
| 05/20/2004 | US20040095265 Semiconductor integrated circuit |
| 05/20/2004 | US20040095181 Nonvolatile selector, and integrated circuit device |
| 05/20/2004 | US20040095178 Pipe latch circuit for outputting data with high speed |
| 05/19/2004 | EP1420414A1 Nonvolatile memory device utilising vertical nanotube |
| 05/19/2004 | EP1287529B8 MULTI-GENERATOR, PARTIAL ARRAY Vt, TRACKING SYSTEM TO IMPROVE ARRAY RETENTION TIME |
| 05/19/2004 | CN1497609A Semiconductor stroage device |
| 05/19/2004 | CN1497607A Circuit and method for supplying page mode operation in semiconductor storing device |
| 05/19/2004 | CN1150623C Semiconductor circuit device |
| 05/19/2004 | CN1150555C Apparatus and method for high-speed wordline driving with low area overheat |
| 05/18/2004 | US6738860 Synchronous DRAM with control data buffer |
| 05/18/2004 | US6738310 Nonvolatile semiconductor memory |
| 05/18/2004 | US6738307 Address structure and methods for multiple arrays of data storage memory |
| 05/18/2004 | US6738306 SRAM cell with single-ended and differential read/write ports |
| 05/18/2004 | US6738301 Method and system for accelerating coupling of digital signals |
| 05/18/2004 | US6738288 Semiconductor memory |
| 05/18/2004 | US6737685 Compact SRAM cell layout for implementing one-port or two-port operation |
| 05/13/2004 | WO2004040579A1 Smart card write-only register |
| 05/13/2004 | US20040090857 Semiconductor device |
| 05/13/2004 | US20040090856 Thin film magnetic memory device for programming required information with an element similar to a memory cell and information programming method |
| 05/13/2004 | US20040090854 Apparatus for and method of controlling AIVC through block selection information in semiconductor memory device |
| 05/13/2004 | US20040090853 Integrated dynamic memory and operating method |
| 05/13/2004 | US20040090825 Read-while-write flash memory devices having local row decoder circuits activated by separate read and write signals |
| 05/13/2004 | US20040089913 Semiconductor memory device with efficiently laid-out internal interconnection lines |
| 05/12/2004 | EP1417686A2 Random-access memory devices comprising a dioded buffer |
| 05/12/2004 | EP1417672A1 Display device comprising an array of pixels allowing storage of data |
| 05/12/2004 | CN1495797A Semiconductor storage equipment with storage unit array which is divided into block |
| 05/11/2004 | US6735668 Process of using a DRAM with address control data |
| 05/11/2004 | US6735667 Synchronous data system with control data buffer |
| 05/11/2004 | US6735147 Semiconductor memory device and a method for generating a block selection signal of the same |
| 05/11/2004 | US6735146 System and method for pulling electrically isolated memory cells in a memory array to a non-floating state |
| 05/11/2004 | US6735145 Method and circuit for optimizing power consumption and performance of driver circuits |
| 05/11/2004 | US6735143 System for reducing power consumption in memory devices |
| 05/11/2004 | US6735128 Data output driver of semiconductor memory device |
| 05/11/2004 | US6735120 Semiconductor device having a high-speed data read operation |
| 05/11/2004 | US6735118 CG-WL voltage boosting scheme for twin MONOS |
| 05/11/2004 | US6735116 NAND-type flash memory device with multi-page program, multi-page read, multi-block erase operations |
| 05/11/2004 | US6735104 Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays |
| 05/11/2004 | US6734066 Method for fabricating split gate flash memory cell |
| 05/06/2004 | US20040085850 Semiconductor memory capable of performing high-speed processing |
| 05/06/2004 | US20040085849 Flash memory, and flash memory access method and apparatus |
| 05/06/2004 | US20040085848 Semiconductor memory device |
| 05/06/2004 | US20040085847 Method and circuit for optimizing power consumption and performance of driver circuits |
| 05/06/2004 | US20040085832 Semiconductor memory device and method of controlling the same |
| 05/06/2004 | US20040085819 Semiconductor integrated circuit device and read start trigger signal generating method therefor |
| 05/06/2004 | US20040085817 First-in first-out memory circuit and method for executing same |
| 05/06/2004 | US20040085814 Nonvolatile semiconductor memory device |
| 05/06/2004 | US20040085804 Synchronous controlled, self-timed local SRAM block |
| 05/06/2004 | US20040085799 Semiconductor memory device with memory cell array divided into blocks |
| 05/06/2004 | EP1416494A2 Semiconductor memory capable of performing high-speed processing |
| 05/06/2004 | EP1416373A2 Method and apparatus to reduce access time in synchronous fifos with zero latency overhead |
| 05/06/2004 | EP1415304A2 Memory device having different burst order addressing for read and write operations |
| 05/04/2004 | US6732226 Memory device for transferring streams of data |
| 05/04/2004 | US6732225 Process for controlling reading data from a DRAM array |
| 05/04/2004 | US6732224 System with control data buffer for transferring streams of data |
| 05/04/2004 | US6731566 Single ended simplex dual port memory cell |
| 05/04/2004 | US6731565 Programmable memory controller and controlling method |
| 05/04/2004 | US6731552 Integrated dynamic memory and operating method |
| 05/04/2004 | US6731549 Semiconductor memory device |
| 05/04/2004 | US6731148 Apparatus and method for generating clock signals |
| 04/29/2004 | US20040083327 Automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards |
| 04/29/2004 | US20040083314 Selector with group identification terminals |
| 04/29/2004 | US20040081013 Latency control circuit and method of latency control |
| 04/29/2004 | US20040080988 Flash EEprom system |
| 04/29/2004 | US20040080970 Semiconductor circuit device with mitigated load on interconnection line |
| 04/29/2004 | US20040080358 Control circuit for selecting the greater of two voltage signals |
| 04/28/2004 | EP1412947A2 Random access decoder |
| 04/28/2004 | CN1147865C Multi-storage-body synchronous semiconductor storage device |
| 04/27/2004 | US6728912 SOI cell stability test method |
| 04/27/2004 | US6728829 Synchronous DRAM system with control data |
| 04/27/2004 | US6728828 Synchronous data transfer system |
| 04/27/2004 | US6728824 Method and apparatus for controlling multi-channel bitstreams |
| 04/27/2004 | US6728819 Synchronous memory device |
| 04/27/2004 | US6728133 Nonvolatile semiconductor memory device |
| 04/27/2004 | US6727876 TFT LCD driver capable of reducing current consumption |
| 04/27/2004 | US6727738 Configuration for generating a clock including a delay circuit and method thereof |
| 04/22/2004 | WO2004034470A2 Dual-port memory cell and layout design |
| 04/22/2004 | WO2004034467A2 Sublithographic nanoscale memory architecture |
| 04/22/2004 | US20040076072 Nonvolatile semiconductor memory device |
| 04/22/2004 | US20040076071 SRAM cell design for soft error rate immunity |
| 04/22/2004 | US20040076070 Semiconductor memory device for enhancing bitline precharge time |
| 04/22/2004 | US20040076069 System and method for initializing a memory device from block oriented NAND flash |
| 04/22/2004 | US20040076068 Method of producing semiconductor integrated circuit device and semiconductor integrated circuit device |
| 04/22/2004 | US20040076067 Method of decreasing instantaneous current without affecting timing |
| 04/22/2004 | US20040076065 Methods of reading and/or writing data to memory devices including virtual ground lines and/or multiple write circuits and related devices |
| 04/22/2004 | US20040076064 Cell circuit for multiport memory using 3-way multiplexer |
| 04/22/2004 | US20040076063 Cell circuit for multiport memory using decoder |
| 04/22/2004 | US20040076055 Delay lock loop circuit useful in a synchronous system and associated methods |
| 04/22/2004 | DE10345481A1 Bitleitungssegmentierung bei Direktzugriffsspeichern Bitleitungssegmentierung in random access memories |
| 04/21/2004 | EP1410399A1 Method and apparatus for decreasing block write operation times performed on nonvolatile memory |
| 04/21/2004 | EP1410396A1 A voltage boost circuit using supply voltage detection to compensate for supply voltage variations in read mode voltages |
| 04/21/2004 | CN1491417A Programmable fuse and antifuse and method thereof |
| 04/21/2004 | CN1490687A Data transmission system and weared communication device |
| 04/21/2004 | CN1146997C Data storage possessing several storage unit |
| 04/21/2004 | CN1146918C Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell |
| 04/20/2004 | US6724682 Nonvolatile semiconductor memory device having selective multiple-speed operation mode |
| 04/20/2004 | US6724679 Semiconductor memory device allowing high density structure or high performance |
| 04/20/2004 | US6724665 Memory device and method for selectable sub-array activation |
| 04/20/2004 | US6724664 Low-amplitude driver circuit |