| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 08/19/2004 | US20040160850 Semiconductor memory devices with driving circuits for screening defective wordlines and related methods |
| 08/19/2004 | US20040160845 Method and apparatus to reduce access time in synchronous FIFOS with zero latency overhead |
| 08/19/2004 | US20040160844 Address structure and methods for multiple arrays of data storage memory |
| 08/19/2004 | US20040160843 Address buffer having (N/2) stages |
| 08/19/2004 | US20040160842 Semiconductor memory device suppressing peak current |
| 08/19/2004 | US20040160838 Memory having variable refresh control and method therefor |
| 08/19/2004 | US20040160822 Thin film magnetic memory device for writing data of a plurality of bits in parallel |
| 08/19/2004 | DE19727087B4 Synchroner graphischer Schreib/Lese-Speicher (RAM) mit Blockschreibsteuerfunktion Synchronous graphic read / write memory (RAM) with block write control function |
| 08/19/2004 | DE10306062B3 Memory module for computer system has separate refresh-control circuit for generation of refresh commands independent of memory controller |
| 08/19/2004 | DE10039612B4 Halbleitervorrichtung mit einem Speicher für eine Zwischenwortgröße A semiconductor device having a memory for an intermediate word size |
| 08/18/2004 | EP1447909A1 Data holding apparatus and data read out method |
| 08/18/2004 | EP1446723A1 Method employed by a base station for transferring data |
| 08/18/2004 | EP1374242B1 Storing an unchanging binary code in an integrated circuit |
| 08/18/2004 | CN1521758A Stack pointer generator and method for generating pointers |
| 08/18/2004 | CN1162914C Multiport static RAM |
| 08/17/2004 | US6779126 Phase detector for all-digital phase locked and delay locked loops |
| 08/17/2004 | US6779074 Memory device having different burst order addressing for read and write operations |
| 08/17/2004 | US6778466 Multi-port memory cell |
| 08/17/2004 | US6778462 Metal-programmable single-port SRAM array for dual-port functionality |
| 08/17/2004 | US6778458 Dram core refresh with reduced spike current |
| 08/17/2004 | US6778451 Semiconductor memory device for masking all bits in a test write operation |
| 08/17/2004 | US6778435 Memory architecture for TCCT-based memory cells |
| 08/17/2004 | US6778434 Magnetic random access memory device with a reduced number of interconnections for selection of address |
| 08/12/2004 | WO2004034470A3 Dual-port memory cell and layout design |
| 08/12/2004 | US20040158757 Interleaved delay line for phase locked and delay locked loops |
| 08/12/2004 | US20040156261 System and method for low area self-timing in memory devices |
| 08/12/2004 | US20040156260 Main word line driver circuit receiving negative voltage in semiconductor memory device |
| 08/12/2004 | US20040156259 Semiconductor memory device |
| 08/12/2004 | US20040156244 Negatively charged wordline for reduced subthreshold current |
| 08/12/2004 | US20040156237 Block select circuit in a flash memory device |
| 08/12/2004 | US20040156228 High density beta ratio independent core cell |
| 08/12/2004 | US20040155343 System and method for row decode in a multiport memory |
| 08/12/2004 | US20040155314 Semiconductor integrated circuits with power reduction mechanism |
| 08/11/2004 | CN1519934A Delay locking loop of reinforced interfrence proof phase swinging of blocking circuit and its method |
| 08/11/2004 | CN1519857A Semiconductor memory appts. having magnetic interference ruduced |
| 08/11/2004 | CN1519852A Memory appts. |
| 08/10/2004 | US6775201 Method and apparatus for outputting burst read data |
| 08/10/2004 | US6775200 Software based memory design generator |
| 08/10/2004 | US6775192 Memory device tester and method for testing reduced power states |
| 08/10/2004 | US6775191 Memory circuit with selective address path |
| 08/10/2004 | US6775179 Memory with shared bit lines |
| 08/10/2004 | US6775177 Semiconductor memory device switchable to twin memory cell configuration |
| 08/10/2004 | US6774892 Display driver IC |
| 08/10/2004 | US6774704 Control circuit for selecting the greater of two voltage signals |
| 08/10/2004 | US6774677 Device for linking a processor to a memory element and memory element |
| 08/10/2004 | US6774673 Level shifter |
| 08/05/2004 | US20040153843 Method for comparing the address of a memory access with an already known address of a faulty memory cell |
| 08/05/2004 | US20040151055 Method for quickly detecting the state of a nonvolatile storage medium |
| 08/05/2004 | US20040151054 Selectable clock input |
| 08/05/2004 | US20040151052 Semiconductor memory device with magnetic disturbance reduced |
| 08/05/2004 | US20040151051 Semiconductor memory device having easily redesigned memory capacity |
| 08/05/2004 | US20040151049 Memory cell with fuse element |
| 08/05/2004 | US20040151047 Register bank |
| 08/05/2004 | US20040151045 Non-volatile memory device |
| 08/05/2004 | US20040151041 Dual port semiconductor memory device |
| 08/05/2004 | US20040151034 Method and circuit for operating a memory cell using a single charge pump |
| 08/05/2004 | US20040151029 Programmable memory cell using charge trapping in a gate oxide |
| 08/05/2004 | US20040151028 Memory array and its peripheral circuit with byte-erase capability |
| 08/05/2004 | US20040151019 Ferroelectric memory |
| 08/05/2004 | US20040150735 Layout technique for address signal lines in decoders including stitched blocks |
| 08/05/2004 | US20040150059 Magnetoresistive memory or sensor devices having improved switching properties and method of fabrication |
| 08/05/2004 | DE10341795A1 Halbleiterspeichervorrichtung A semiconductor memory device |
| 08/04/2004 | CN1518225A 小功率逻辑门 Low-power logic gates |
| 08/04/2004 | CN1518114A 半导体存储器 Semiconductor memory |
| 08/04/2004 | CN1517905A 信息系统 Information system |
| 08/03/2004 | US6772277 Method of writing to a memory array using clear enable and column clear signals |
| 08/03/2004 | US6771559 Non-volatile semiconductor integrated circuit |
| 08/03/2004 | US6771557 Predecode column architecture and method |
| 08/03/2004 | US6771555 Row access information transfer device using internal wiring of a memory cell array |
| 08/03/2004 | US6771526 Method and apparatus for data transfer |
| 08/03/2004 | US6771192 Method and system for DC-balancing at the physical layer |
| 07/29/2004 | US20040145963 Semiconductor device including duty cycle correction circuit |
| 07/29/2004 | US20040145961 Portable device having a universal unique identifier |
| 07/29/2004 | US20040145959 Semiconductor memory device with reduced current consumption during standby state |
| 07/29/2004 | US20040145958 Multiple configuration multiple chip memory device and method |
| 07/29/2004 | US20040144994 Apparatus and methods for optically-coupled memory systems |
| 07/29/2004 | DE102004002437A1 Verzögerungsregelkreis, integrierte Schaltung und Betriebsverfahren Delay locked loop, integrated circuit and method of operation |
| 07/28/2004 | EP1441442A1 A low power logic gate |
| 07/28/2004 | EP1441360A1 Negative-voltage word line decoder with small area terminating elements |
| 07/28/2004 | CN1516192A Semiconductor storage device with delayed automatic precharge function and related method thereof |
| 07/28/2004 | CN1159854C Interleave address generator and method thereof |
| 07/28/2004 | CN1159723C Serial memroy |
| 07/27/2004 | US6769050 Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules |
| 07/27/2004 | US6768698 Semiconductor memory device with internal clock generation circuit |
| 07/27/2004 | US6768696 Semiconductor memory device in which data are read and written asynchronously with application of address signal |
| 07/27/2004 | US6768688 Semiconductor memory device having booster circuits |
| 07/27/2004 | US6768361 Clock synchronization circuit |
| 07/27/2004 | US6767816 Method for making a three-dimensional memory array incorporating serial chain diode stack |
| 07/27/2004 | US6767655 Magneto-resistive element |
| 07/22/2004 | WO2004061859A2 Stochastic assembly of sublithographic nanoscale interfaces |
| 07/22/2004 | WO2004061853A2 Method of address individual memory devices on a memory module |
| 07/22/2004 | US20040143700 Processor system using synchronous dynamic memory |
| 07/22/2004 | US20040141403 Semiconductor memory device |
| 07/22/2004 | US20040141400 Low power logic gate |
| 07/22/2004 | US20040141397 Asynchronous interface circuit and method for a pseudo-static memory device |
| 07/22/2004 | US20040141393 Method and apparatus for selecting memory cells within a memory array |
| 07/22/2004 | US20040141384 Method and system for selecting redundant rows and columns of memory cells |
| 07/22/2004 | US20040140828 Circuit for detecting a logic transition with improved stability of the length of a detection signal pulse |
| 07/21/2004 | EP1438720A2 Storage assembly |
| 07/21/2004 | CN1158670C Bi-directional shift register |