| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 09/12/2002 | US20020125933 Method of and apparatus for correctly transmitting signals at high speed without waveform distortion |
| 09/12/2002 | US20020125926 Delay lock loop and update method with limited drift and improved power savings |
| 09/12/2002 | US20020125499 Semiconductor device with circuitry for efficient information exchange |
| 09/12/2002 | DE10204822A1 Eingabe-/Ausgabeleitungs-Abtastverstärker eines Halbleiterspeicherbauelementes Input / output line sense amplifier of a semiconductor memory device |
| 09/11/2002 | EP1239594A2 Semiconductor device with circuitry for efficient information exchange |
| 09/11/2002 | EP1239487A1 Memory reset method and circuit |
| 09/11/2002 | EP1238393A2 Mobile communication device having integrated embedded flash and sram memory |
| 09/11/2002 | CN2510963Y Digital music playing machine with encrypting function |
| 09/11/2002 | CN1368734A Semiconductor memory capable of control work timing of read amplifier |
| 09/10/2002 | US6449727 High-speed data transfer synchronizing system and method |
| 09/10/2002 | US6449707 Information processing unit, information processing structure unit, information processing structure, memory structure unit and semiconductor memory device |
| 09/10/2002 | US6449679 RAM controller interface device for RAM compatibility (memory translator hub) |
| 09/10/2002 | US6449674 Internal command signal generator and method therefor |
| 09/10/2002 | US6449210 Semiconductor memory array architecture |
| 09/10/2002 | US6449209 Semiconductor memory device comprising more than two internal banks of different sizes |
| 09/10/2002 | US6449204 Dynamic semiconductor memory device capable of rearranging data storage from a one bit/one cell scheme in a normal mode to a one bit/two cell scheme in a twin-cell mode for lengthening a refresh interval |
| 09/10/2002 | US6449203 Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs |
| 09/10/2002 | US6449202 DRAM direct sensing scheme |
| 09/10/2002 | US6449201 Semiconductor memory device having a hierarchical bit line architecture |
| 09/10/2002 | US6449198 Semiconductor memory device |
| 09/10/2002 | US6449196 Bus driving circuit and memory device having same |
| 09/10/2002 | US6449194 Multiplexer with dummy switches in normally off state to increase operating speed |
| 09/10/2002 | US6449193 Burst access memory system |
| 09/10/2002 | US6449191 Current-mode sense amplifier with low power consumption |
| 09/10/2002 | US6449182 Low-power semiconductor memory device |
| 09/10/2002 | US6448849 Semiconductor devices including a switch mounted thereon and a module loaded with the same |
| 09/10/2002 | US6448615 Methods, structures, and circuits for transistors with gate-to-body capacitive coupling |
| 09/06/2002 | WO2002069496A2 Differential input buffer bias pulser |
| 09/06/2002 | WO2002069344A2 Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory |
| 09/06/2002 | WO2002069343A1 Magnetoresistive midpoint generator |
| 09/06/2002 | WO2002069341A2 A method of synchronizing read timing in a high speed memory system |
| 09/06/2002 | WO2002069340A1 Non-destructive readout |
| 09/06/2002 | WO2002054405A8 Memory architecture with controllable bitline lengths |
| 09/05/2002 | US20020124153 Memory component with multiple transfer formats |
| 09/05/2002 | US20020124130 Memory controller and method using logical/physical address control table |
| 09/05/2002 | US20020122348 Data input circuit and method for synchronous semiconductor memory device |
| 09/05/2002 | US20020122347 Synchronous-reading nonvolatile memory |
| 09/05/2002 | US20020122346 High speed signal path and method |
| 09/05/2002 | US20020122344 Sense amplifiers having reduced Vth deviation |
| 09/05/2002 | US20020122335 Burst access memory system |
| 09/05/2002 | US20020121886 Methods to make DRAM fully compatible with SRAM |
| 09/05/2002 | DE10107835A1 Vorrichtung mit einem Speicherelement und Speicherelement Device comprising a memory element and memory element |
| 09/05/2002 | DE10107833A1 Computer memory arrangement, such as a bust-flash memory, has buffer memories for both command and data memories to speed operation of a bus interface |
| 09/05/2002 | DE10107314A1 Verfahren zum Lesen einer Speicherzelle eines Halbleiterspeichers und Halbleiterspeicher A method of reading a memory cell of a semiconductor memory and semiconductor memory |
| 09/04/2002 | EP1237160A2 Sense amplifier control circuit of semiconductor memory device |
| 09/04/2002 | EP0960373B1 Method and apparatus for maintaining a time order by physical ordering in a memory |
| 09/04/2002 | EP0830685B1 Single-ended sensing using global bit lines for dram |
| 09/04/2002 | CN1367491A Integrated circuit storage equipment with multiport ultrahigh speed buffer storage array and its operation method |
| 09/03/2002 | US6446159 Semiconductor circuit and method of controlling the same |
| 09/03/2002 | US6446158 Memory system using FET switches to select memory banks |
| 09/03/2002 | US6445800 Audio signal reproducing apparatus |
| 09/03/2002 | US6445644 Apparatus and method for generating a clock within a semiconductor device and devices and systems including same |
| 09/03/2002 | US6445643 Method and apparatus for setting write latency |
| 09/03/2002 | US6445642 Synchronous double data rate DRAM |
| 09/03/2002 | US6445641 Memory device with time shared data lines |
| 09/03/2002 | US6445636 Method and system for hiding refreshes in a dynamic random access memory |
| 09/03/2002 | US6445634 Serial access memory and data write/read method |
| 09/03/2002 | US6445633 Read amplifier circuit for high-speed reading and semiconductor memory device employing the read amplifier circuit |
| 09/03/2002 | US6445632 Semiconductor memory device for fast access |
| 09/03/2002 | US6445629 Method of stressing a memory device |
| 09/03/2002 | US6445627 Semiconductor integrated circuit |
| 09/03/2002 | US6445624 Method of synchronizing read timing in a high speed memory system |
| 09/03/2002 | US6445622 Voltage level shifter circuit and nonvolatile semiconductor storage device using the circuit |
| 09/03/2002 | US6445621 Dynamic data amplifier with built-in voltage level shifting |
| 09/03/2002 | US6445610 Variable voltage isolation gate and method |
| 09/03/2002 | US6445608 Ferroelectric random access memory configurable output driver circuit |
| 09/03/2002 | US6445234 Apparatus and method for accelerating initial lock time of delayed locked loop |
| 09/03/2002 | US6445231 Digital dual-loop DLL design using coarse and fine loops |
| 09/03/2002 | US6445216 Sense amplifier having reduced Vt mismatch in input matched differential pair |
| 08/29/2002 | WO2002067265A2 Electronic circuit and method for accessing non-volatile memory |
| 08/29/2002 | WO2002067264A2 Method for reading a memory cell of a semiconductor memory, and semiconductor memory |
| 08/29/2002 | WO2002039231A3 Media storage device management |
| 08/29/2002 | WO2001012862A9 Compositions and methods for preparing oligonucleotide solutions |
| 08/29/2002 | US20020118592 Differential input buffer bias pulser |
| 08/29/2002 | US20020118590 Semiconductor memory device with low power consumption |
| 08/29/2002 | US20020118578 Method of synchronizing read timing in a high speed memory system |
| 08/29/2002 | US20020118577 Semiconductor memory device and data read method thereof |
| 08/29/2002 | US20020118576 Signal amplification circuit for amplifying and sensing current difference and semiconductor memory device including same |
| 08/29/2002 | US20020118575 Semiconductor device |
| 08/29/2002 | US20020118567 Serial storage device |
| 08/29/2002 | US20020118307 Method for controlling memory in digital system |
| 08/29/2002 | US20020118306 Method for controlling memory in digital system |
| 08/29/2002 | US20020118047 Input-output line sense ampifier having small currnet consumption and direct current |
| 08/29/2002 | DE10206060A1 Speichersystem mit Stichleitungskonfiguration und zugehöriges Datenübertragungsverfahren Storage system with stub configuration and associated data transmission method |
| 08/29/2002 | DE10158714A1 Halbleiterspeicher mit Spiegelfunktion Semiconductor memory with mirror function |
| 08/29/2002 | DE10148904A1 Vorrichtung und Verfahren zur Steuerung der Abtastverstärkerfreigabe in einem Halbleiterspeicherbauelement Apparatus and method for controlling the Abtastverstärkerfreigabe in a semiconductor memory device |
| 08/29/2002 | DE10145153A1 Halbleiterspeichervorrichtung mit steuerbarer Operationszeit des Leseverstärkers A semiconductor memory device having a controllable operating time of the sense amplifier |
| 08/29/2002 | DE10105285A1 Halbleiterspeicher mit Precharge-Steuerung Semiconductor memory with precharge control |
| 08/29/2002 | DE10104701A1 Verfahren zum Einschreiben von Daten und Speicheranordnung A method for writing data and memory array |
| 08/28/2002 | EP1235349A1 Evaluation of conduction at precharged node |
| 08/28/2002 | EP1235155A2 Semiconductor memory device and information processing unit |
| 08/28/2002 | EP1234305A1 A portable data storage device |
| 08/28/2002 | EP1066637B1 Multi-level data through a single input/output pin |
| 08/28/2002 | CN1366677A Reference cell for huigh speed sensing in non-volatile memories |
| 08/27/2002 | US6442716 Data output buffer |
| 08/27/2002 | US6442644 Memory system having synchronous-link DRAM (SLDRAM) devices and controller |
| 08/27/2002 | US6442297 Storage apparatus and writing and/or reading methods for use in hierarchical coding |
| 08/27/2002 | US6442103 Synchronous SRAM device with late write function |
| 08/27/2002 | US6442102 Method and apparatus for implementing high speed DDR SDRAM read interface with reduced ACLV effects |
| 08/27/2002 | US6442100 Integrated memory |