| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 09/25/2002 | CN1371515A Electric/electronic circuit device |
| 09/25/2002 | CN1371175A Command input circuit with command acquisition unit |
| 09/24/2002 | US6457110 Method of accessing syncronous dynamic random access memory in scanner |
| 09/24/2002 | US6457108 Method of operating a system-on-a-chip including entering a standby state in a non-volatile memory while operating the system-on-a-chip from a volatile memory |
| 09/24/2002 | US6457095 Method and apparatus for synchronizing dynamic random access memory exiting from a low power state |
| 09/24/2002 | US6457094 Memory array architecture supporting block write operation |
| 09/24/2002 | US6456563 Semiconductor memory device that operates in sychronization with a clock signal |
| 09/24/2002 | US6456562 Clock generation circuits |
| 09/24/2002 | US6456561 Synchronous semiconductor memory device |
| 09/24/2002 | US6456557 Voltage regulator for memory device |
| 09/24/2002 | US6456553 Circuit configuration for switching over a receiver circuit in particular in DRAM memories and DRAM memory having the circuit configuration |
| 09/24/2002 | US6456551 Semiconductor memory device having prefetch operation mode and data transfer method for reducing the number of main data lines |
| 09/24/2002 | US6456549 Sense amplifier circuit and semiconductor storage device |
| 09/24/2002 | US6456548 Sense amplifier circuit and semiconductor storage device |
| 09/24/2002 | US6456547 Semiconductor memory device with function of repairing stand-by current failure |
| 09/24/2002 | US6456546 Repair circuit using antifuse |
| 09/24/2002 | US6456545 Method and apparatus for data transmission and reception |
| 09/24/2002 | US6456544 Selective forwarding of a strobe based on a predetermined delay following a memory read command |
| 09/24/2002 | US6456543 Data input/output circuit for semiconductor memory device |
| 09/24/2002 | US6456542 Synchronous memory status register |
| 09/24/2002 | US6456540 Method and apparatus for gating a global column select line with address transition detection |
| 09/24/2002 | US6456539 Method and apparatus for sensing a memory signal from a selected memory cell of a memory device |
| 09/24/2002 | US6456538 Nonvolatile memory, system having nonvolatile memories, and data read method of the system |
| 09/24/2002 | US6456517 System having memory devices operable in a common interface |
| 09/24/2002 | US6456157 Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits |
| 09/24/2002 | US6456130 Delay lock loop and update method with limited drift and improved power savings |
| 09/24/2002 | US6456129 Internal clock signal generator |
| 09/24/2002 | US6456121 Sense amplifier for integrated circuits using PMOS transistors |
| 09/24/2002 | US6456120 Capacitor-coupling differential logic circuit |
| 09/19/2002 | WO2002073658A2 Yield and speed enhancement of semiconductor integrated circuits using post-fabrication transistor mismatch compensation circuitry |
| 09/19/2002 | WO2002073619A2 System latency levelization for read data |
| 09/19/2002 | WO2002073618A2 Memory sense amplifier for a semiconductor memory device |
| 09/19/2002 | US20020133742 DRAM memory page operation method and its structure |
| 09/19/2002 | US20020133731 Duty cycle distortion compensation for the data output of a memory device |
| 09/19/2002 | US20020133667 Method of accessing syncronous dynamic random access memory in scanner |
| 09/19/2002 | US20020133666 System latency levelization for read data |
| 09/19/2002 | US20020133665 Burst/pipelined edo memory device |
| 09/19/2002 | US20020131535 Circuit and method for reducing noise interference in digital differential input receivers |
| 09/19/2002 | US20020131320 SRAM emulator |
| 09/19/2002 | US20020131319 Digital delay, digital phase shifter |
| 09/19/2002 | US20020131316 Semiconductor memory device and method of pre-charging I/O lines |
| 09/19/2002 | US20020131315 Multi-bank memory |
| 09/19/2002 | US20020131314 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions |
| 09/19/2002 | US20020131313 High frequency range four bit prefetch output data path |
| 09/19/2002 | US20020131312 Pseudo differential sensing method and apparatus for DRAM cell |
| 09/19/2002 | US20020131311 Balanced sense amplifier control for open digit line architecture memory devices |
| 09/19/2002 | US20020131308 Semiconductor Memory |
| 09/19/2002 | US20020131305 Semiconductor memory device |
| 09/19/2002 | US20020131298 Evaluation of conduction at precharged node |
| 09/19/2002 | US20020131293 BIT line sense amplifier suppressing a pull-up voltage of a BIT signal and semiconductor memory device having the same |
| 09/19/2002 | US20020130876 Pixel pages using combined addressing |
| 09/19/2002 | US20020130794 Encoded bits over interconnects |
| 09/19/2002 | US20020130691 Method and apparatus for fast lock of delay lock loop |
| 09/19/2002 | US20020130682 Adaptive threshold logic circuit |
| 09/19/2002 | US20020130424 Semiconductor integrated circuit |
| 09/19/2002 | DE10110625A1 Valuating read-out signal of read-out amplifier for dynamic semiconductor memory |
| 09/18/2002 | EP1241676A1 Pseudo differential sensing method and apparatus for dram cell |
| 09/18/2002 | EP1040484B1 Method and system for processing pipelined memory commands |
| 09/17/2002 | US6453425 Method and apparatus for switching clocks presented to synchronous SRAMs |
| 09/17/2002 | US6453402 Method for synchronizing strobe and data signals from a RAM |
| 09/17/2002 | US6453401 Memory controller with timing constraint tracking and checking unit and corresponding method |
| 09/17/2002 | US6453400 Semiconductor integrated circuit device |
| 09/17/2002 | US6453399 Semiconductor memory device and computer having a synchronization signal indicating that the memory data output is valid |
| 09/17/2002 | US6453381 DDR DRAM data coherence scheme |
| 09/17/2002 | US6452867 Full page increment/decrement burst for DDR SDRAM/SGRAM |
| 09/17/2002 | US6452866 Method and apparatus for multiple latency synchronous dynamic random access memory |
| 09/17/2002 | US6452865 Method and apparatus for supporting N-bit width DDR memory interface using a common symmetrical read data path with 2N-bit internal bus width |
| 09/17/2002 | US6452864 Interleaved memory device for sequential access synchronous reading with simplified address counters |
| 09/17/2002 | US6452863 Method of operating a memory device having a variable data input length |
| 09/17/2002 | US6452861 Semiconductor memory device allowing simultaneous inputting of N data signals |
| 09/17/2002 | US6452855 DRAM array interchangeable between single-cell and twin-cell array operation |
| 09/17/2002 | US6452850 Read amplifier subcircuit for a DRAM memory |
| 09/17/2002 | US6452846 Driver circuit for a voltage-pulling device |
| 09/17/2002 | US6452845 Apparatus for testing redundant elements in a packaged semiconductor memory device |
| 09/17/2002 | US6452841 Dynamic random access memory device and corresponding reading process |
| 09/17/2002 | US6452838 Nonvolatile memory system, semiconductor memory and writing method |
| 09/17/2002 | US6452833 Semiconductor memory device |
| 09/17/2002 | US6452832 DRAM circuit and method of controlling the same |
| 09/17/2002 | US6452824 Semiconductor memory device |
| 09/17/2002 | US6452432 Signal processing circuits having a pair of delay locked loop (DLL) circuits for adjusting a duty-cycle of a periodic digital signal and methods of operating same |
| 09/14/2002 | CA2376902A1 Sram emulator |
| 09/14/2002 | CA2340804A1 Sram emulator |
| 09/12/2002 | WO2002071407A2 Asynchronous, high-bandwidth memory component using calibrated timing elements |
| 09/12/2002 | US20020129194 Method and device for operating a RAM memory |
| 09/12/2002 | US20020129193 Tri-stating output buffer during initialization of synchronous memory |
| 09/12/2002 | US20020126565 Semiconductor integrated circuit device with internal clock generating circuit |
| 09/12/2002 | US20020126564 Semiconductor memory device having different data rates in read operation and write operation |
| 09/12/2002 | US20020126563 Interleaved memory device for sequential access synchronous reading with simplified address counters |
| 09/12/2002 | US20020126562 Memory circuitry for programmable logic integrated circuit devices |
| 09/12/2002 | US20020126560 Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs |
| 09/12/2002 | US20020126559 Refresh controller and address remapping circuit and method for dual mode full/reduced density drams |
| 09/12/2002 | US20020126558 Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs |
| 09/12/2002 | US20020126557 Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMS |
| 09/12/2002 | US20020126556 Refresh controller and address remapping circuit and method for dual mode full/ reduced density drams |
| 09/12/2002 | US20020126555 Precharge circuit with small width |
| 09/12/2002 | US20020126550 Redundant memory circuit for analog semiconductor memory |
| 09/12/2002 | US20020126544 Method and apparatus for protecting appliance memory contents |
| 09/12/2002 | US20020126542 Device having a memory element, and a memory element |
| 09/12/2002 | US20020126541 Method and apparatus for processing commands in a queue coupled to a system or memory |
| 09/12/2002 | US20020126540 Multiplexer with dummy switches in normally off state to increase operating speed |