Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
12/2002
12/11/2002CN1096082C High-speed synchronous mask ROM with pipeline structure
12/10/2002USRE37930 DRAM including an address space divided into individual blocks having memory cells activated by row address signals
12/10/2002US6493794 Large scale FIFO circuit
12/10/2002US6493789 Memory device which receives write masking and automatic precharge information
12/10/2002US6493787 Device, system and method for accessing plate-shaped memory
12/10/2002US6493286 tRCD margin
12/10/2002US6493285 Method and apparatus for sampling double data rate memory read data
12/10/2002US6493282 Semiconductor integrated circuit
12/10/2002US6493278 Semiconductor device and control device for use therewith
12/10/2002US6493275 Semiconductor integrated circuit device and electronic equipment
12/10/2002US6493274 Data transfer circuit and semiconductor integrated circuit having the same
12/10/2002US6493272 Data holding circuit having backup function
12/10/2002US6493271 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein
12/10/2002US6493267 Nonvolatile semiconductor memory device having verify function
12/10/2002US6492852 Pre-divider architecture for low power in a digital delay locked loop
12/10/2002US6492844 Single-ended sense amplifier with sample-and-hold reference
12/10/2002US6492706 Programmable pin flag
12/10/2002US6492211 Method for novel SOI DRAM BICMOS NPN
12/05/2002US20020184592 Semiconductor memory device
12/05/2002US20020184579 System and method for recognizing and configuring devices embedded on memory modules
12/05/2002US20020184459 Digital camera memory system
12/05/2002US20020184456 Interleaver memory access apparatus and method of mobile communication system
12/05/2002US20020184452 Embedded memory access method and system for application specific integrated circuits
12/05/2002US20020184437 Memory architecture for supporting concurrent access of different types
12/05/2002US20020184431 Method and apparatus for low power memory bit line precharge
12/05/2002US20020181639 Adaptive de-skew clock generation
12/05/2002US20020181339 Information reproduction apparatus and information reproduction
12/05/2002US20020181318 Semiconductor storage unit
12/05/2002US20020181317 Trcd margin
12/05/2002US20020181316 System to set burst mode in a device
12/05/2002US20020181307 Single bitline direct sensing architecture for high speed memory device
12/05/2002US20020181305 Trcd margin
12/05/2002US20020181298 Semiconductor memory with a signal path
12/05/2002US20020181297 Method of controlling a delay locked loop
12/05/2002US20020181296 Method of characterizing a delay locked loop
12/05/2002US20020181295 TRCD margin
12/05/2002US20020181294 TRCD margin
12/05/2002US20020181293 Trcd margin
12/05/2002US20020181290 Data output interface, in particular for semiconductor memories
12/05/2002US20020181289 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein
12/05/2002US20020181277 Method and circuit for timing dynamic reading of a memory cell with control of the integration time
12/05/2002US20020181266 Steering gate and bit line segmentation in non-volatile memories
12/05/2002US20020180589 Comparator circuits having non-complementary input structures
12/05/2002US20020180543 Clock generation circuits and integrated circuit memory devices for controlling a clock period based on temperature and methods for using the same
12/05/2002US20020180516 Data receiver technology
12/05/2002US20020180501 Digital dual-loop DLL design using coarse and fine loops
12/05/2002US20020180500 Clock generation circuit, control method of clock generation circuit, clock reproducing circuit, semiconductor memory device, and dynamic random access memory
12/05/2002US20020180499 Method for generating internal clock of semiconductor memory device and circuit thereof
12/05/2002US20020180491 Sense amplifier circuit of semiconductor memory device
12/05/2002US20020179943 Semiconductor integrated circuit device
12/05/2002DE10121837C1 Speicherschaltung mit mehreren Speicherbereichen A memory circuit comprising a plurality of memory areas
12/04/2002EP1262990A1 Memory architecture for supporting concurrent access of different types
12/04/2002EP1262989A1 System to set burst mode in a device
12/04/2002EP1262988A2 Embedded memory access method and system for application specific integrated circuits
12/04/2002EP1262969A2 Information reproduction apparatus and information reproduction method
12/04/2002EP1183690B1 Memory array with address scrambling
12/04/2002EP1118081B1 Integrated memory with differential read amplifier
12/04/2002EP0893799B1 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein
12/04/2002CN1383153A 多口存储单元结构 Multi-port memory cell structure
12/04/2002CN1095584C Storage interface accessing circuit and method for storage accessing
12/03/2002US6490669 Memory LSI with compressed data inputting and outputting function
12/03/2002US6490646 Integrated circuit device made secure by means of additional bus lines
12/03/2002US6490235 Storage and reproduction apparatus with rotary control element for controlling operations
12/03/2002US6490225 Memory having a synchronous controller and asynchronous array and method thereof
12/03/2002US6490224 Delay-locked loop with binary-coupled capacitor
12/03/2002US6490221 Semiconductor memory device with low power consumption
12/03/2002US6490219 Semiconductor integrated circuit device and method of manufacturing thereof
12/03/2002US6490214 Semiconductor memory device
12/03/2002US6490212 Bitline precharge matching
12/03/2002US6490211 Random access memory device
12/03/2002US6490207 Delay-locked loop with binary-coupled capacitor
12/03/2002US6490206 High-speed synchronous semiconductor memory having multi-stage pipeline structure and operating method
12/03/2002US6489823 Semiconductor device capable of generating highly precise internal clock
12/03/2002US6489822 Delay locked loop with delay control unit for noise elimination
11/2002
11/28/2002WO2002095761A2 Apparatus and method for memory storage cell leakage cancellation scheme
11/28/2002WO2002095760A1 Semiconductor memory
11/28/2002WO2002095758A1 Dynamically configurated storage array with improved data access
11/28/2002WO2002069341A3 A method of synchronizing read timing in a high speed memory system
11/28/2002WO2002005281A9 A high speed dram architecture with uniform access latency
11/28/2002US20020178413 Time data compression technique for high speed integrated circuit memory devices
11/28/2002US20020178324 High performance cost optimized memory
11/28/2002US20020176447 Method and device for initialising an asynchronous latch chain
11/28/2002US20020176316 Semiconductor memory and method for operating the semiconductor memory
11/28/2002US20020176315 Synchronous mirror delay with reduced delay line taps
11/28/2002US20020176311 RAM having dynamically switchable access modes
11/28/2002US20020176309 Controlling output current in rambus DRAM
11/28/2002US20020176308 Semiconductor integrated circuit device with memory blocks and a write buffer capable of storing write data from an external interface
11/28/2002US20020176307 Bank control circuit in rambus DRAM and semiconductor memory device thereof
11/28/2002US20020176303 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
11/28/2002US20020176302 Cell data protection circuit in semiconductor memory device and method of driving refresh mode
11/28/2002US20020176298 Memory cell read device
11/28/2002US20020176292 Semiconductor integrated circuit device
11/28/2002US20020176291 Method for providing a low power read only memory banking methodology with efficient bus muxing
11/28/2002US20020176275 Alternating reference wordline scheme for fast dram
11/28/2002US20020175773 Circuit for preventing system malfunction in semiconductor memory and method thereof
11/28/2002US20020175707 Circuit technique for high speed low power data transfer bus
11/28/2002US20020175702 Digital designs optimized with time division multiple access technology
11/28/2002DE10161128A1 Mit einem Taktsignal synchron arbeitende Halbleiterspeichervorrichtung With a clock signal synchronously operating the semiconductor memory device
11/28/2002DE10124278A1 Integrated memory e.g. SDRAM has controller to receive configuration value containing latency and burst access values based on received access commands
11/27/2002EP1260988A2 Resistive cross point memory device with calibration controller for a sense amplifier
1 ... 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 ... 532