| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 01/02/2003 | US20030002336 Distributed write data drivers for burst access memories |
| 01/02/2003 | US20030002328 SRAM device |
| 01/02/2003 | US20030002320 Memory device |
| 01/02/2003 | US20030002319 Apparatus and method for pumping memory cells in a memory |
| 01/02/2003 | US20030002316 Semiconductor device |
| 01/02/2003 | US20030002315 Low-power semiconductor memory device |
| 01/02/2003 | US20030001679 Sub-ranging wide-bandwidth low noise PLL architecture |
| 01/02/2003 | US20030001665 Integrated circuit for receiving a clock signal, particularly for a semiconductor memory circuit |
| 01/02/2003 | US20030001651 Programmable delay line and corresponding memory |
| 01/02/2003 | US20030001631 Gate coupled voltage support for an output driver circuit |
| 01/02/2003 | US20030001629 Signal transmission circuit capable of tolerating high-voltage input signal |
| 01/02/2003 | US20030001624 Method and input circuit for evaluating a data signal at an input of a memory component |
| 01/02/2003 | US20030001621 Data I/O circuit of semiconductor memory device |
| 01/02/2003 | US20030001233 semiconductor memory device |
| 01/02/2003 | US20030001208 Methods, structures, and circuits for transistors with gate-to-body capacitive coupling |
| 01/02/2003 | EP1271651A2 SRAM device |
| 01/02/2003 | EP1271551A2 Semiconductor memory device and information device |
| 01/02/2003 | EP1271545A1 Bit line pre-charging system and semiconductor storage device using the same |
| 01/02/2003 | EP1271544A1 Charging circuit and semiconductor memory device using the same |
| 01/02/2003 | EP1271543A2 Method and system for fast memory access |
| 01/02/2003 | EP1271542A2 Method and system for fast data access using a memory array |
| 01/02/2003 | EP1271541A2 Data storing circuit and data processing apparatus |
| 01/02/2003 | EP1271540A2 Semiconductor memory device, information apparatus, and method for determining access period for semiconductor memory device |
| 01/02/2003 | EP1271399A1 Data carrier with integrated circuit |
| 01/02/2003 | EP1269476A2 Synchronous flash memory |
| 01/02/2003 | EP1269474A2 Symmetrical protection scheme for first and last sectors of synchronous flash memory |
| 01/02/2003 | EP1269473A2 Synchronous flash memory with non-volatile mode register |
| 01/02/2003 | EP1269472A2 Elimination of precharge operation in synchronous flash memory |
| 01/02/2003 | EP1034463A4 Method and apparatus for audibly indicating when a predetermined location has been encountered in stored data |
| 01/02/2003 | EP0836195B1 Video camera system and semiconductor image memory circuit applied to it |
| 01/01/2003 | CN1388534A Data writing method of semiconductor memory and semiconductor memory |
| 12/31/2002 | USRE37944 Single chip frame buffer and graphics accelerator |
| 12/31/2002 | US6502161 Memory system including a point-to-point linked memory subsystem |
| 12/31/2002 | US6501701 Semiconductor memory device |
| 12/31/2002 | US6501699 Refresh control for semiconductor memory device |
| 12/31/2002 | US6501698 Structure and method for hiding DRAM cycle time behind a burst access |
| 12/31/2002 | US6501697 High density memory sense amplifier |
| 12/31/2002 | US6501696 Current steering reduced bitline voltage swing, sense amplifier |
| 12/31/2002 | US6501695 Technique for the reduction of memory access time variation |
| 12/31/2002 | US6501694 Precharge circuit with small width |
| 12/31/2002 | US6501688 tRCD margin |
| 12/31/2002 | US6501687 Bitline pull-up circuit for compensating leakage current |
| 12/31/2002 | US6501675 Alternating reference wordline scheme for fast DRAM |
| 12/31/2002 | US6501672 Dynamic random access memory (DRAM) capable of canceling out complementary noise developed in plate electrodes of memory cell capacitors |
| 12/31/2002 | US6501670 High speed memory architecture and busing |
| 12/31/2002 | US6501668 Semiconductor memory device |
| 12/31/2002 | US6501308 Generation of clock signals for a semiconductor memory that are edge-synchronous with the output signals of a clock generator |
| 12/31/2002 | US6501306 Data output circuit for semiconductor device with level shifter and method for outputting data using the same |
| 12/31/2002 | US6501302 Single-input/dual-output sense amplifier |
| 12/27/2002 | WO2002103911A2 Method and apparatus for a clock circuit |
| 12/27/2002 | WO2002029817A3 Upscaled clock feeds memory to make parallel waves |
| 12/26/2002 | US20020199128 Data transfer control method, and peripheral circuit, data processor and data processing system for the method |
| 12/26/2002 | US20020199042 First-in, first-out memory system and method thereof |
| 12/26/2002 | US20020196885 Determining phase relationships using digital phase values |
| 12/26/2002 | US20020196700 Write data masking for higher speed drams |
| 12/26/2002 | US20020196699 Method and apparatus for setting write latency |
| 12/26/2002 | US20020196698 Symmetric segmented memory array architecture |
| 12/26/2002 | US20020196695 Column multiplexer for semiconductor memories |
| 12/26/2002 | US20020196694 Circuit for generating control signal using make-link type fuse |
| 12/26/2002 | US20020196692 Proportional to temperature voltage generator |
| 12/26/2002 | US20020196690 Semiconductor memory device |
| 12/26/2002 | US20020196689 Semiconductor memory device and data read method thereof |
| 12/26/2002 | US20020196685 Trusted and verifiable data storage system, method, apparatus and device |
| 12/26/2002 | US20020196682 Memory device |
| 12/26/2002 | US20020196678 Eliminating store/restores within hot function prolog/epilogs using volatile regosters |
| 12/26/2002 | US20020196675 Write data masking for higher speed drams |
| 12/26/2002 | US20020196674 Semiconductor memory device |
| 12/26/2002 | US20020196669 Decoding scheme for a stacked bank architecture |
| 12/26/2002 | US20020196668 Distributed write data drivers for burst access memories |
| 12/26/2002 | US20020196667 Read circuit of nonvolatile semiconductor memory |
| 12/26/2002 | US20020196666 Electronic device with locally reduced effects on analog signals |
| 12/26/2002 | US20020196664 Biasing circuit for multi-level memory cells |
| 12/26/2002 | US20020196659 Non-Volatile memory |
| 12/26/2002 | US20020196074 Semiconductor integrated circuit |
| 12/26/2002 | US20020196059 Memory system including a memory device having a controlled output driver characteristic |
| 12/26/2002 | US20020196035 Digitally controlled adaptive driver for sensing capacitive load |
| 12/26/2002 | US20020195678 Semiconductor integrated circuit device |
| 12/25/2002 | CN2528080Y Chip group and controller for supporting information signal interruption |
| 12/24/2002 | US6499089 Method, architecture and circuitry for independently configuring a multiple array memory device |
| 12/24/2002 | US6499084 Digital recording and reproducing apparatus capable of determining whether data was rewritten or not |
| 12/24/2002 | US6499081 Method and apparatus for determining a longest prefix match in a segmented content addressable memory device |
| 12/24/2002 | US6498766 Integrated circuit memory devices that utilize indication signals to increase reliability of reading and writing operations and methods of operating same |
| 12/24/2002 | US6498765 Semiconductor integrated circuit |
| 12/24/2002 | US6498758 Twisted bitlines to reduce coupling effects (dual port memories) |
| 12/24/2002 | US6498755 Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other |
| 12/24/2002 | US6498524 Input/output data synchronizing device |
| 12/24/2002 | US6498522 Semiconductor device |
| 12/24/2002 | US6498520 Minimizing the effect of clock skew in precharge circuit |
| 12/24/2002 | US6498516 Minimizing the effect of clock skew in bit line write driver |
| 12/24/2002 | US6498510 Adaptive threshold logic circuit |
| 12/24/2002 | US6497370 Input circuit for memory smart cards |
| 12/24/2002 | CA2080299C Data security arrangement for semiconductor programmable logic devices |
| 12/19/2002 | WO2002101748A2 Sense amplifier and architecture for open digit arrays |
| 12/19/2002 | WO2002101747A2 Draw with bit line precharging, inverting data writing, retained data output and reduced power consumption |
| 12/19/2002 | WO2002101746A2 Sense amplifier with improved latching |
| 12/19/2002 | WO2002045094A3 Method and apparatus for built-in self-repair of memory storage arrays |
| 12/19/2002 | WO2001075896A9 Flash with consistent latency for read operations |
| 12/19/2002 | US20020194450 Apparatus and structure for rapid enablement |
| 12/19/2002 | US20020194446 Data transfer control method, and peripheral circuit, data processor and data processing system for the method |
| 12/19/2002 | US20020194425 Method and apparatus for integrated circuit with DRAM |