| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 08/14/2002 | DE10200685A1 Halbleiterspeichervorrichtung mit mehr als zwei internen Bänken unterschiedlicher Größen A semiconductor memory device with more than two internal banks of different sizes |
| 08/14/2002 | DE10104262A1 Leseverstärkeranordnung für eine Speichereinrichtung Sense amplifier configuration for a memory device |
| 08/14/2002 | CN1364298A System and method for displaying information on screen of user interface device under control of digital audio playback device |
| 08/14/2002 | CN1363935A Semiconductor storaging device for shortening test time |
| 08/13/2002 | US6434736 Location based timing scheme in memory design |
| 08/13/2002 | US6434661 Synchronous semiconductor memory including register for storing data input and output mode information |
| 08/13/2002 | US6434657 Method and apparatus for accommodating irregular memory write word widths |
| 08/13/2002 | US6434103 Recording medium, recording apparatus, recording method, editing apparatus and editing method |
| 08/13/2002 | US6434083 Semiconductor memory device for implementing high speed operation of delay locked loop |
| 08/13/2002 | US6434082 Clocked memory device that includes a programming mechanism for setting write recovery time as a function of the input clock |
| 08/13/2002 | US6434081 Calibration technique for memory devices |
| 08/13/2002 | US6434079 Semiconductor memory device for distributing load of input and output lines |
| 08/13/2002 | US6434077 Method and apparatus for selectively disabling logic in a semiconductor device |
| 08/13/2002 | US6434076 Refresh control circuit for low-power SRAM applications |
| 08/13/2002 | US6434075 Semiconductor circuit device with reduced power consumption in slow operation mode |
| 08/13/2002 | US6434074 Sense amplifier imbalance compensation for memory self-timed circuits |
| 08/13/2002 | US6434072 Row decoded biasing of sense amplifier for improved one's margin |
| 08/13/2002 | US6434071 Circuit and method of selectively activating feedback devices for local bit lines in a memory |
| 08/13/2002 | US6434069 Two-phase charge-sharing data latch for memory circuit |
| 08/13/2002 | US6434065 Semiconductor memory device of low power consumption |
| 08/13/2002 | US6434062 Delay locked loop for use in semiconductor memory device |
| 08/13/2002 | US6434061 Circuit configuration for enhancing performance characteristics of fabricated devices |
| 08/13/2002 | US6434060 Write pulse limiting for worm storage device |
| 08/13/2002 | US6434058 Semiconductor integrated circuit |
| 08/13/2002 | US6434057 Memory device with a sense amplifier detection circuit to control an output buffer amplifier |
| 08/13/2002 | US6434056 Set of two memories on the same monolithic integrated circuit |
| 08/13/2002 | US6434055 Nonvolatile semiconductor memory device |
| 08/13/2002 | US6434048 Pulse train writing of worm storage device |
| 08/13/2002 | US6434034 Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems |
| 08/13/2002 | US6433607 Input circuit and semiconductor integrated circuit having the input circuit |
| 08/13/2002 | US6433600 Method and apparatus for glitch protection for input buffers in a source-synchronous environment |
| 08/13/2002 | US6433593 Gate coupled voltage support for an output driver circuit |
| 08/13/2002 | US6433590 Current mirror type sense amplifier circuits for semiconductor memory devices and methods of operating same |
| 08/13/2002 | US6433589 Sense amplifier and method for sensing signals in a silicon-on-insulator integrated circuit |
| 08/13/2002 | US6433569 Apparatus for testing an integrated circuit in an oven during burn-in |
| 08/13/2002 | US6433521 Source and sink voltage regulator using one type of power transistor |
| 08/13/2002 | US6433405 Integrated circuit having provisions for remote storage of chip specific operating parameters |
| 08/08/2002 | WO2002061754A1 Semiconductor memory and method for entering its operation mode |
| 08/08/2002 | WO2001093273A3 Semiconductor memory with programmable bitline multiplexers |
| 08/08/2002 | US20020108054 Solid-state memory device storing program code and methods for use therewith |
| 08/08/2002 | US20020108024 Method for protecting publicly distributed software |
| 08/08/2002 | US20020108018 Memory module control and status |
| 08/08/2002 | US20020108013 Address wrap function for addressable memory devices |
| 08/08/2002 | US20020105853 Memory access methods and devices for use with random access memories |
| 08/08/2002 | US20020105850 Semiconductor memory device and signal line arrangement method thereof |
| 08/08/2002 | US20020105846 High speed dram local bit line sense amplifier |
| 08/08/2002 | US20020105844 Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division |
| 08/08/2002 | US20020105843 Semiconductor device with self refresh test mode |
| 08/08/2002 | US20020105842 Semiconductor memory device having improved data transfer rate without providing a register for holding write data |
| 08/08/2002 | US20020105838 Synchronous semiconductor memory device performing data output in synchronization with external clock |
| 08/08/2002 | US20020105836 Method and device for storing and outputting data with a virtual channel |
| 08/08/2002 | US20020105826 SRAM device |
| 08/08/2002 | US20020105822 Method for arranging wiring line including power reinforcing line and semiconductor device having power reinforcing line |
| 08/08/2002 | US20020105635 Semiconductor memory device |
| 08/08/2002 | US20020105367 Phase adjustor for semiconductor integrated circuit device |
| 08/08/2002 | US20020105097 PAD arrangement in semiconductor memory device and method of driving semiconductor device |
| 08/08/2002 | US20020104872 Method and apparatus for securing electronic circuits |
| 08/08/2002 | DE10106817C1 Speicheranordnung Memory array |
| 08/08/2002 | DE10102350A1 Integrierter Speicher mit mehreren Speicherzellenfeldern sowie Verfahren zum Betrieb des integrierten Speichers Integrated memory having a plurality of memory cell arrays and methods for operating the integrated memory |
| 08/07/2002 | EP1229551A2 Method and apparatus for storing data in an integrated circuit |
| 08/07/2002 | CN1362708A Read-write method for flash memory chip |
| 08/07/2002 | CN1088897C Decoder for high density ROM addrss bus |
| 08/06/2002 | US6430651 Memory device for constituting a memory subsystem of a data processing apparatus |
| 08/06/2002 | US6430242 Initialization system for recovering bits and group of bits from a communications channel |
| 08/06/2002 | US6430103 Semiconductor integrated circuit device with memory banks and read buffer capable of storing data read out from one memory bank when data of another memory bank is outputting |
| 08/06/2002 | US6430099 Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operation |
| 08/06/2002 | US6430097 Semiconductor memory device enabling reduction of test time period |
| 08/06/2002 | US6430095 Method for cell margin testing a dynamic cell plate sensing memory architecture |
| 08/06/2002 | US6430091 Semiconductor memory device having reduced current consumption at internal boosted potential |
| 08/06/2002 | US6430089 Semiconductor device |
| 08/06/2002 | US6430078 Low-voltage digital ROM circuit and method |
| 08/06/2002 | US6430077 Method for regulating read voltage level at the drain of a cell in a symmetric array |
| 08/06/2002 | US6430076 Multi-level signal lines with vertical twists |
| 08/06/2002 | US6429703 Output circuit for high-frequency transmission applications |
| 08/01/2002 | WO2002059899A2 Mram bit line word line architecture |
| 08/01/2002 | WO2002059897A1 Multiple ports memory-cell structure |
| 08/01/2002 | WO2002059794A2 System and method of discovering information |
| 08/01/2002 | US20020103962 Data transfer system and data transfer method |
| 08/01/2002 | US20020103961 Semiconductor integrated circuit and data processing system |
| 08/01/2002 | US20020101906 Method for determining the temperature of a semiconductor component |
| 08/01/2002 | US20020101777 Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox |
| 08/01/2002 | US20020101774 Semiconductor memory device with controllable operation timing of sense amplifier |
| 08/01/2002 | US20020101773 Semiconductor memory device having intermediate voltage generating circuit |
| 08/01/2002 | US20020101768 Enhanced compact memory card with write protaction |
| 08/01/2002 | US20020101766 Method and apparatus for gating a global column select line with address transition detection |
| 08/01/2002 | US20020101758 Design methodology for sensing resistance values of memory cells |
| 08/01/2002 | US20020101712 Diskette type electronic device |
| 08/01/2002 | CA2436594A1 System and method of discovering information |
| 07/31/2002 | EP1227499A1 Non-volatile electrically alterable semiconductor memory |
| 07/31/2002 | EP1092193A4 Architecture for a universal serial bus-based pc flash disk |
| 07/31/2002 | CN1361532A Disassembling panel compression type digital music broadcasting machine |
| 07/30/2002 | US6427197 Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations |
| 07/30/2002 | US6426916 Memory device having a variable data output length and a programmable register |
| 07/30/2002 | US6426915 Fast cycle RAM and data readout method therefor |
| 07/30/2002 | US6426914 Floating wordline using a dynamic row decoder and bitline VDD precharge |
| 07/30/2002 | US6426912 Test circuit for testing semiconductor memory |
| 07/30/2002 | US6426905 High speed DRAM local bit line sense amplifier |
| 07/30/2002 | US6426900 Synchronous semiconductor memory device performing data output in synchronization with external clock |
| 07/30/2002 | US6426692 Data transfer method for a scanning identification system |
| 07/30/2002 | US6426657 Sense-amplifying circuit |