Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
06/2002
06/27/2002US20020079543 Semiconductor device with output latch circuit outputting complementary data at high speed
06/27/2002DE10061243A1 Data propagation time determination method for databus in semiconductor memory has time interval between transfer of data to output buffer and transfer to output altered in dependence on data comparison
06/27/2002DE10059553A1 Schaltungsanordnung und Verfahren zum Synchronisieren Circuit arrangement and method for synchronizing
06/26/2002EP1217744A1 An output buffer with constant switching current
06/26/2002EP1217628A1 Method and system to adjust an internal temporisation or any other characteristic in an integrated circuit and integrated circuit thereof
06/26/2002EP1217625A2 Removable face plate compressed digital music player
06/26/2002EP1216476A1 Self-erasing memory cell
06/26/2002EP1216471A1 Musical instrument digital recording device with interference
06/26/2002CN2497397Y Digital recording/playing and word processing apparatus
06/26/2002CN1355922A Memory array with address scrambling
06/26/2002CN1355538A Integrated circuit device capable of extension memory
06/26/2002CN1355536A Semiconductor memory device with multiple low-pissipation module type
06/26/2002CN1086817C Method for connecting DRAM module to DRAM exchange control system
06/25/2002US6412072 Parasitically powered microprocessor capable of transmitting data over a single data line and ground
06/25/2002US6412052 Method and apparatus for detecting an initialization signal and a command packet error in packetized dynamic random access memories
06/25/2002US6412041 Real time processing method of a flash memory
06/25/2002US6411564 Semiconductor memory device and synchronous memory
06/25/2002US6411563 Semiconductor integrated circuit device provided with a logic circuit and a memory circuit and being capable of efficient interface between the same
06/25/2002US6411560 Semiconductor memory device capable of reducing leakage current flowing into substrate
06/25/2002US6411559 Semiconductor memory device including a sense amplifier
06/25/2002US6411557 Memory architecture with single-port cell and dual-port (read and write) functionality
06/25/2002US6411555 Reference charge generator, a method for providing a reference charge from a reference charge generator, a method of operating a reference charge generator and a dram memory circuit formed using memory cells having an area of 6f2
06/25/2002US6411553 Single ended data bus equilibration scheme
06/25/2002US6411550 Semiconductor integrated-circuit device
06/25/2002US6411549 Reference cell for high speed sensing in non-volatile memories
06/25/2002US6411543 Dynamic random access memory (RAM), semiconductor storage device, and semiconductor integrated circuit (IC) device
06/25/2002US6411140 Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit
06/25/2002US6411131 Method for differentiating a differential voltage signal using current based differentiation
06/25/2002US6411128 Logical circuit for serializing and outputting a plurality of signal bits simultaneously read from a memory cell array or the like
06/25/2002US6410955 Comb-shaped capacitor for use in integrated circuits
06/20/2002WO2002049034A2 Amplifier for reading storage cells with exclusive-or type function
06/20/2002US20020078468 Data processor for outputting data according to their types
06/20/2002US20020078311 Multi-port memory based on DRAM core
06/20/2002US20020078294 High-speed random access semiconductor memory device
06/20/2002US20020077834 Removable face plate compressed digital music player
06/20/2002US20020076872 Method for masking DQ bits
06/20/2002US20020075968 Method and apparatus for generating multi-level reference voltage in systems using equalization or crosstalk cancellation
06/20/2002US20020075748 Input circuit for an integrated memory
06/20/2002US20020075747 Delayed locked loop implementation in a synchronous dynamic random access memory
06/20/2002US20020075746 Fast accessible dynamic type semiconductor memory device
06/20/2002US20020075745 Power up initialization circuit responding to an input signal
06/20/2002US20020075742 Circuits and method for multi-level data through a single input/output pin
06/20/2002US20020075741 Circuit configuration for generating sense amplifier control signals
06/20/2002US20020075738 Recording/reproducing device and a recording medium able to read from computers
06/20/2002US20020075734 Digital memory structure and device, and methods for the management thereof
06/20/2002US20020075732 Semiconductor memory device
06/20/2002US20020075731 Semiconductor memory device having internal data read circuit excellent in noise immunity
06/20/2002US20020075729 Bitline pull-up circuit for compensating leakage current
06/20/2002US20020075724 Non-volatile memory with power standby
06/20/2002US20020075720 Semiconductor memory device having plate lines and precharge circuits
06/20/2002US20020075715 Memory device, method of accessing the memory device, and Reed-Solomon decoder including the memory device
06/20/2002US20020075048 Timing signal generating circuit
06/20/2002US20020075047 Configuration for generating a clock including a delay circuit and method thereof
06/20/2002DE10144245A1 Semiconductor memory device e.g. high integrated DRAM, includes isolator connected bitline of one block and precharger connected to complementary bitline, are synchronously controlled by control signal
06/19/2002EP1215682A2 Initializing an integrated circuit using compressed data from a remote fusebox
06/19/2002EP1215678A2 Semiconductor memory, and memory access method
06/18/2002USRE37753 Semiconductor memory device and read and write methods thereof
06/18/2002US6408372 Data processing control device
06/18/2002US6408356 Apparatus and method for modifying signals from a CPU to a memory card
06/18/2002US6407963 Semiconductor memory device of DDR configuration having improvement in glitch immunity
06/18/2002US6407962 Memory module having data switcher in high speed memory device
06/18/2002US6407961 Dual access memory array
06/18/2002US6407957 Semiconductor memory
06/18/2002US6407956 Semiconductor memory device
06/18/2002US6407951 Pulse generator circuit and semiconductor memory provided with the same
06/18/2002US6407950 Semiconductor memory device capable of implementing redundancy-based repair efficiently in relation to layout and operating speed and semiconductor integrated circuit device having such semiconductor memory device
06/18/2002US6407949 Mobile communication device having integrated embedded flash and SRAM memory
06/18/2002US6407588 High speed low power input buffer
06/18/2002US6407580 Latch sense amplifier circuit with an improved next stage buffer
06/13/2002WO2002046873A2 System and method for managing information objects
06/13/2002WO2002017327A3 Memory device having posted write per command
06/13/2002US20020073273 Memory module with DRAM package for matching channel impedance
06/13/2002US20020073269 Data-recording-medium controller, data-recording-medium control method, data-recording apparatus and data-recording-apparatus control unit
06/13/2002US20020072818 MPEG portable sound reproducing system and a reproducing method thereof
06/13/2002US20020071335 Circuit configuration and method for synchronization
06/13/2002US20020071332 Semiconductor memory device and data processing system having semiconductor memory device
06/13/2002US20020071331 Power-saving modes for memories
06/13/2002US20020071327 Memory device with reduced refresh noise
06/13/2002US20020071321 System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories
06/13/2002US20020071319 Method and apparatus for data transmission and reception
06/13/2002US20020071317 Integrated memory having memory cells and reference cells, and corresponding operating method
06/13/2002US20020071316 Methods and apparatus for reading memory device register data
06/13/2002US20020071302 Semiconductor memory with multistage local sense amplifier
06/13/2002US20020070771 Semiconductor controller device having a controlled output driver characteristic
06/13/2002US20020070762 Amplifier for use in semiconductor integrated circuits
06/13/2002US20020070757 Buffer circuit for the reception of a clock signal
06/13/2002DE10060124A1 Operating data processing system involves setting changeover bit before internal read operation to permit copying of original memory contents to shadow memory, then clearing bit
06/13/2002DE10058966A1 Charging memory cells involves selecting memory cells and carrying out refresh process only for selected memory cells; memory cells can be selected by area of memory
06/13/2002DE10058965A1 RAM memory has at least some cells with additional device for activation by forced control voltage different from normal control voltage to impose defined logical state on memory cells
06/13/2002DE10058324A1 Eingangsschaltung für einen integrierten Speicher Input circuit for an integrated memory
06/13/2002DE10056164C1 Schaltungsanordnung zur Erzeugung von mit Ausgangssignalen eines Taktgenerators flankensynchronen Taktsignalen für einen Halbleiterspeicher Circuitry for generating edge synchronous with output signals of a clock generator clock signals for a semiconductor memory
06/13/2002CA2436636A1 System and method for managing information objects
06/12/2002EP1212754A1 Electric/electronic circuit device
06/12/2002CN1353853A Semiconductor memory card, apparatus for recording data onto semiconductor memory card and apparatus for reproducing data of semiconductor memory card
06/12/2002CN1353460A Data storage possessing sereral storage unit
06/12/2002CN1353456A Input/output element assembling method and semi-conductor equipment
06/11/2002US6405324 Circuit and method for masking a dormant memory cell
06/11/2002US6405297 Automatic reloading of serial read pipeline on last bit transfers to serial access memory
06/11/2002US6405296 Asynchronous request/synchronous data dynamic random access memory
06/11/2002US6405293 Selectively accessible memory banks for operating in alternately reading or writing modes of operation