Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
12/2002
12/19/2002US20020194424 Multiport memory, data processor and data processing system
12/19/2002US20020194416 Information processing system with memory modules of a serial bus architecture
12/19/2002US20020192892 Method and circuit for generating reference voltages for reading a multilevel memory cell
12/19/2002US20020191480 Clock synchronous semiconductor memory device
12/19/2002US20020191479 Semiconductor memory device operable for both of CAS latencies of one and more than one
12/19/2002US20020191477 A write circuit of a memory deivce
12/19/2002US20020191476 Semiconductor integrated circuit device and data writing method therefor
12/19/2002US20020191466 System and method for performing partial array self-refresh operation in a semiconductor memory device
12/19/2002US20020191463 Row decoded biasing of sense amplifier for improved one's margin
12/19/2002US20020191462 Controller for delay locked loop circuits
12/19/2002US20020191461 Reduced area sense amplifier isolation layout in a dynamic RAM architecture
12/19/2002US20020191457 Memory architecture with single-port cell and dual-port (read and write) functionality)
12/19/2002US20020191456 Information storage medium, information recording method and information processing method
12/19/2002US20020191455 Memory cell arrangement and method for its fabricating it
12/19/2002US20020191449 Method of controlling a delay locked loop
12/19/2002US20020191448 Timing circuit and method for a compilable dram
12/19/2002US20020191446 Semiconductor memory device having self-timing circuit
12/19/2002US20020191437 Magnetic memory device
12/19/2002US20020191435 Method for non-destructive readout and apparatus for use with the method
12/19/2002US20020191433 Memory structures having selectively disabled portions for power conservation
12/19/2002US20020190772 Method and apparatus for a clock circuit
12/19/2002US20020190767 Power reduction for delay locked loop circuits
12/19/2002US20020190761 Bus circuit preventing delay of the operational speed and design method thereof
12/19/2002US20020190708 Memory device tester and method for testing reduced power states
12/19/2002DE10220328A1 Schaltung zur Taktsignalerzeugung, zugehörige integrierte Schaltkreisbauelemente und Auffrischtaktsteuerverfahren Circuit for clock signal generation, associated integrated circuit devices and Auffrischtaktsteuerverfahren
12/19/2002DE10128996A1 Process and device to monitor the memory cells of a volatile data store has independent monitoring coupled with the operational function
12/19/2002DE10126802A1 Data bus procedure adjusts source clock delays to suit module characteristics
12/19/2002DE10126604C1 Production of memory cell array, e.g. dynamic random access memory, includes stages for contacting superimposed selective transistor and memory capacitor
12/19/2002DE10126115A1 Datenausgabeschnittstelle, insbesondere für Halbleiterspeicher Data output interface, in particular for semiconductor memories
12/19/2002CA2447650A1 Sense amplifier with improved latching
12/18/2002EP1267354A2 Semiconductor memory device, method for controlling same, and electronic information apparatus
12/18/2002EP1267353A2 Semiconductor integrated circuit device and data writing method therefor
12/18/2002EP1267272A2 A specialized memory device
12/18/2002EP1266381A1 Method and apparatus for an easy identification of a state of a dram generator controller
12/18/2002EP1166273B1 Disposable sound recording and reproduction device
12/18/2002EP1163677B1 Integrated memory with memory cells and reference cells and corresponding operating method
12/18/2002CN1385905A Magnetic RAM of transistor with vertical structure and making method thereof
12/18/2002CN1385859A Electric resistance cross-point memory utilizing checking amplifier demarcating method on chip
12/18/2002CN1385858A Method for sensing non-volatility ferroelectric internal memory
12/18/2002CN1096749C 5V tolerant input/output circuit
12/18/2002CN1096712C Output driver for mixed supply voltage systems
12/18/2002CN1096683C Semiconductor storage device with data output path for quick access
12/18/2002CN1096680C 半导体存储装置 The semiconductor memory device
12/18/2002CN1096679C 动态存储器 Dynamic Memory
12/18/2002CN1096655C Multichip integrated circuit (IC) card and IC card system using same
12/17/2002US6496897 Semiconductor memory device which receives write masking information
12/17/2002US6496610 Data processing apparatus having DRAM incorporated therein
12/17/2002US6496446 Semiconductor memory device having burst readout mode and data readout method
12/17/2002US6496445 Semiconductor memory device having altered clock frequency for address and/or command signals, and memory module and system having the same
12/17/2002US6496444 Elimination of precharge operation in synchronous flash memory
12/17/2002US6496443 Data buffer control circuits, integrated circuit memory devices and methods of operation thereof using read cycle initiated data buffer clock signals
12/17/2002US6496442 Dynamic random access memory device and semiconductor integrated circuit device
12/17/2002US6496437 Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory
12/17/2002US6496435 Sense amplifier control circuit of semiconductor memory device
12/17/2002US6496434 Differential sensing in a memory using two cycle pre-charge
12/17/2002US6496431 Semiconductor integrated circuit
12/17/2002US6496430 Semiconductor memory circuit having selective redundant memory cells
12/17/2002US6496427 Nonvolatile semiconductor memory device
12/17/2002US6496424 Method and apparatus for generating and controlling integrated circuit memory write signals
12/17/2002US6496420 Methods and apparatus for reading memory device register data
12/17/2002US6496403 Semiconductor memory device
12/17/2002US6496402 Noise suppression for open bit line DRAM architectures
12/17/2002US6496051 Output sense amplifier for a multibit memory cell
12/17/2002US6496043 Method and apparatus for measuring the phase of captured read data
12/17/2002US6496032 Method and structure for efficiently placing and interconnecting circuit blocks in an integrated circuit
12/12/2002WO2002099810A1 Semiconductor device
12/12/2002WO2002099808A1 Steering gate and bit line segmentation in non-volatile memories
12/12/2002WO2002099807A2 Method and apparatus for boosting bitlines for low vcc read
12/12/2002WO2002099661A2 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
12/12/2002US20020188816 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
12/12/2002US20020188812 Implementing a dual partition flash with suspend/resume capabilities
12/12/2002US20020187620 Mask ROM and method for manufacturing the same
12/12/2002US20020186717 Method and system for deskewing parallel bus channels to increase data transfer rates
12/12/2002US20020186608 High frequency range four bit prefetch output data path
12/12/2002US20020186607 Sense amplifier and architecture for open digit arrays
12/12/2002US20020186600 Column repair circuit and method of using nonvolatile ferroelectric memory device
12/12/2002US20020186598 Semiconductor circuit device with improved special mode
12/12/2002US20020186596 Semiconductor device with data output circuit having slew rate adjustable
12/12/2002US20020186595 Semiconductor device having a plurality of output signals
12/12/2002US20020186593 Semiconductor memory device
12/12/2002US20020186591 Semiconductor memory device having memory cell arrays capable of accomplishing random access
12/12/2002US20020186590 Nonvolatile semiconductor memory device having hierarchical sector structure
12/12/2002US20020186583 Recessed magnetic storage element and method of formation
12/12/2002US20020186579 Static RAM with optimized timing of driving control signal for sense amplifier
12/12/2002US20020186051 Sense amplifier with improved latching
12/12/2002DE10225398A1 Halbleiterspeichervorrichtung mit Speicherzellenarrays, die zum Durchführen eines wahlfreien Zugriffs in der Lage ist A semiconductor memory device comprising memory cell arrays, which is for performing a random access in a position
12/12/2002DE10158310A1 Schaltung und Verfahren zur Spaltenreparatur bei einem nichtflüchtigen ferroelektrischen Speicher Circuit and method for column repair in a non-volatile ferroelectric memory
12/12/2002DE10127371A1 Semiconducting memory arrangement has read amplifiers combined into groups; amplifiers in each group can be connected via data bus associated with group to corresponding global bit line
12/12/2002DE10126312A1 Halbleiterspeicher mit einem Signalpfad A semiconductor memory comprising a signal path
12/12/2002DE10125911A1 Testing of proprietary or manufacturer memory modules with a device that allows such modules to be tested with a standard system board, thus considerably lowering testing costs
12/12/2002DE10125371A1 Halbleiterspeicher und Verfahren zum Betrieb des Halbleiterspeichers A semiconductor memory and method of operating the semiconductor memory
12/12/2002DE10124753A1 Reading out, storing binary memory cell signals involves connecting binary intermediate signal to main data line pair(s) depending on line control signal, outputting via main data line pair
12/11/2002EP1265433A1 Digital memory system
12/11/2002EP1265287A2 Non-volatile memory
12/11/2002EP1265247A1 A programmable delay line and corresponding memory
12/11/2002EP1264313A2 Memory module with hierarchical functionality
12/11/2002EP1264190A1 Circuit and method for evaluating capacitors in matrices
12/11/2002CN1384964A 便携式数据存储装置 The portable data storage device
12/11/2002CN1384506A Automatic partial-array updating system and method for semiconductor memory
12/11/2002CN1384504A Low-voltage conrol method and device
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