| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 07/11/2002 | US20020089870 Ferroelectric memory |
| 07/11/2002 | US20020089869 Discontinuity-based memory cell sensing |
| 07/11/2002 | US20020089509 Memory device having depth compare-write function and method for depth compare-write used by the memory device |
| 07/11/2002 | US20020089476 TFT LCD driver capable of reducing current consumption |
| 07/11/2002 | US20020089375 Bit line voltage regulation circuit |
| 07/11/2002 | US20020089361 Compensation for a delay locked loop |
| 07/11/2002 | US20020088960 Semiconductor memory device having a word line enable sensing circuit |
| 07/11/2002 | DE10162193A1 Semiconductor memory device for processing internal command signals, addresses and data input/output uses an internal timing signal inverted by an external timing signal, logical combination circuits and clock pulse generators. |
| 07/11/2002 | DE10136163A1 Konfiguration zur Erzeugung eines Taktes mit einer Verzögerungsschaltung und ein Verfahren hierfür Configuration for generating a clock having a delay circuit and a method thereof |
| 07/11/2002 | DE10126597A1 Halbleitereinrichtung mit Ausgangslatchschaltung zur Ausgabe von Komplementärdaten mit hoher Geschwindigkeit Semiconductor device with output latch to issue complementary data at high speed |
| 07/11/2002 | DE10062110A1 Method for writing an item of data into a memory cell in a memory cell section uses addressable column and line wires, amplifying circuits linked to the column wires and a loading alignment device to align loading on the column wires. |
| 07/10/2002 | CN1357893A Method and device of using compressed data in far-end fuse box to initialize integrated circuit |
| 07/10/2002 | CN1357891A Semiconductor memory and its access method |
| 07/10/2002 | CN1357889A Synchronous memory module with optional clock terminal and memory system thereof |
| 07/10/2002 | CN1087473C Semiconductor memory device having cache function |
| 07/10/2002 | CN1087472C Dynamical memory |
| 07/09/2002 | US6418078 Synchronous DRAM device having a control data buffer |
| 07/09/2002 | US6418077 Memory access methods and devices for use with random access memories |
| 07/09/2002 | US6418073 Semiconductor memory device |
| 07/09/2002 | US6418071 Method of testing a memory cell |
| 07/09/2002 | US6418070 Memory device tester and method for testing reduced power states |
| 07/09/2002 | US6418064 Sense amplifier output control circuit |
| 07/09/2002 | US6418063 Memory architecture and systems and methods using the same |
| 07/09/2002 | US6418057 Nonvolatile semiconductor memory device capable of correctly performing erasure/programming completion determination even in presence of defective bit |
| 07/09/2002 | US6418044 Method and circuit for determining sense amplifier sensitivity |
| 07/09/2002 | US6417715 Clock generation circuit generating internal clock of small variation in phase difference from external clock, and semiconductor memory device including such clock generation circuit |
| 07/09/2002 | US6417704 Power-on circuit and resetting method |
| 07/09/2002 | US6417698 Linearized digital phase-locked loop method |
| 07/09/2002 | US6417697 Circuit technique for high speed low power data transfer bus |
| 07/09/2002 | US6417530 Sense amplifier layout method, and semiconductor memory device using the same |
| 07/04/2002 | WO2002052570A1 Techniques to synchronously operate a synchronous memory |
| 07/04/2002 | WO2001075623A3 Zero-latency-zero bus turnaround synchronous flash memory |
| 07/04/2002 | US20020087911 Source synchronous bus |
| 07/04/2002 | US20020087826 Address counter and address counting method |
| 07/04/2002 | US20020087817 Interlaced memory device with random or sequential access |
| 07/04/2002 | US20020087805 Method of maintaining data coherency in late-select synchronous pipeline type semiconductor memory device and data coherency maintaining circuit therefor |
| 07/04/2002 | US20020087790 Memory integrated circuit device which samples data upon detection of a strobe signal |
| 07/04/2002 | US20020087782 Read/write amplifier for a DRAM memory cell, and DRAM memory |
| 07/04/2002 | US20020087777 Synchronous integrated circuit device |
| 07/04/2002 | US20020087768 Valid data strobe detection technique |
| 07/04/2002 | US20020087750 Variable input/output control device in synchronous semiconductor device |
| 07/04/2002 | US20020086477 Apparatus and a method for a data output circuit in a semiconductor memory |
| 07/04/2002 | US20020085655 High-speed serial data recovery |
| 07/04/2002 | US20020085445 Semiconductor memory device enabling reduction of test time period |
| 07/04/2002 | US20020085443 Apparatus for selecting bank in semiconductor memory device |
| 07/04/2002 | US20020085442 Semiconductor integrated circuit device |
| 07/04/2002 | US20020085440 Sensing circuit for magnetic memory unit |
| 07/04/2002 | US20020085437 Memory architecture for micromirror cell |
| 07/04/2002 | US20020085430 Semiconductor memory device using dedicated command and address strobe signal and associated method |
| 07/04/2002 | US20020085428 Arrangement of bitline boosting capacitor in semiconductor memory device |
| 07/04/2002 | US20020085427 Semiconductor memory device for variably controlling drivability |
| 07/04/2002 | US20020085426 Apparatus for varying data input/output path in semiconductor memory device |
| 07/04/2002 | US20020085417 Burst access memory with zero wait states |
| 07/04/2002 | US20020085405 Memory architecture with controllable bitline lengths |
| 07/04/2002 | US20020084857 Delay locked loop for improving high frequency characteristics and yield |
| 07/04/2002 | US20020084807 Asynchronous FIFO circuit and method of reading and writing data through asynchronous FIFO circuit |
| 07/04/2002 | US20020084334 Digital electronic audio player with cassette tape simulation feature and compatible with cassette tape players, and method therefore |
| 07/03/2002 | EP1220226A2 Multi-port memory based on DRAM core |
| 07/03/2002 | EP1220225A1 Method and device for reducing the mean access time to a non volatile memory during the reading phase |
| 07/03/2002 | EP1220222A1 Mobile karaoke system, method for ensuring electromagnetic compatibility of said karaoke system, mobile wireless transmitter for said system, method for preventing the use of unauthorized cartridges and restraining unauthorized access to said system |
| 07/03/2002 | EP1220217A2 Data reproduction system, data recorder and data reader preventing fraudulent usage by monitoring reproducible time limit |
| 07/03/2002 | EP1218888A2 A symmetric segmented memory array architecture |
| 07/03/2002 | EP1218545A2 Compositions and methods for preparing oligonucleotide solutions |
| 07/03/2002 | EP1141959B1 Integrated memory |
| 07/03/2002 | CN1356698A Prompting or warning memo recorder with automatic induction |
| 07/02/2002 | US6415390 Method and apparatus for controlling the data rate of a clocking circuit |
| 07/02/2002 | US6415340 Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths |
| 07/02/2002 | US6415339 Memory device having a plurality of programmable internal registers and a delay time register |
| 07/02/2002 | US6415007 Charge pump having two sub charge pumps which include a common charge/discharge terminal |
| 07/02/2002 | US6414903 Method and apparatus for crossing clock domain boundaries |
| 07/02/2002 | US6414902 Use of setup time to send signal through die |
| 07/02/2002 | US6414899 Limited swing driver circuit |
| 07/02/2002 | US6414898 Method to reduce peak current for RAS cycle sensing in DRAM using non-multiplexed row and column addresses to avoid damage to battery |
| 07/02/2002 | US6414897 Local write driver circuit for an integrated circuit device incorporating embedded dynamic random access memory (DRAM) |
| 07/02/2002 | US6414894 Semiconductor device with reduced current consumption in standby state |
| 07/02/2002 | US6414892 Semiconductor memory device |
| 07/02/2002 | US6414891 Semiconductor device including complementary data bus pair |
| 07/02/2002 | US6414884 Method and apparatus for securing electronic circuits |
| 07/02/2002 | US6414883 Semiconductor memory device |
| 07/02/2002 | US6414880 Multiple line buffer type memory LSI |
| 07/02/2002 | US6414879 Semiconductor memory device |
| 07/02/2002 | US6414874 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| 07/02/2002 | US6414533 Over-voltage tolerant, active pull-up clamp circuit for a CMOS crossbar switch |
| 07/02/2002 | US6414530 Semiconductor integrated circuit device, semiconductor memory system and clock synchronous circuit |
| 07/02/2002 | US6414521 Sense amplifier systems and methods |
| 07/02/2002 | US6414300 Circuit with a sensor and non-volatile memory having a ferroelectric dielectric capacitor |
| 06/27/2002 | WO2001091128A3 Semiconductor memory and controlling method thereof |
| 06/27/2002 | US20020083295 Semiconductor memory |
| 06/27/2002 | US20020083289 Circuit and method for controlling buffers in semiconductor memory device |
| 06/27/2002 | US20020083286 Techniques to asynchronously operate a synchronous memory |
| 06/27/2002 | US20020083284 Data reproduction system, data recorder and data reader preventing fraudulent usage by monitoring reproducible time limit |
| 06/27/2002 | US20020082791 Method and system for the adjustment of an internal timing signal or a corresponding reference in an integrated circuit, and corresponding integrated circuit |
| 06/27/2002 | US20020081789 Sense amplifier circuit for semiconductor device |
| 06/27/2002 | US20020080672 First-in first-out memory device and method of generating flag signal in the same |
| 06/27/2002 | US20020080671 Circuits and methods for multi-level data through a single input/output pin |
| 06/27/2002 | US20020080670 Semiconductor memory device |
| 06/27/2002 | US20020080664 Semiconductor device |
| 06/27/2002 | US20020080640 Dynamic RAM-and semiconductor device |
| 06/27/2002 | US20020079931 Sense amplifier drive circuit |
| 06/27/2002 | US20020079928 Using a timing strobe for synchronization and validation in a digital logic device |