Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
10/2002
10/17/2002US20020149971 Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other
10/17/2002US20020149970 Bus driving circuit and memory device having same
10/17/2002US20020149969 Bus driving circuit and memory device having same
10/17/2002US20020149968 Data holding circuit having backup function
10/17/2002US20020149967 Data strobe gating for source synchronous communications interface
10/17/2002US20020149965 Method and circuit for dynamic reading of a memory cell at low supply voltage and with low output dynamics
10/17/2002US20020149964 Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell
10/17/2002US20020149961 Semiconductor memory device
10/17/2002US20020149960 Memory device with prefetched data ordering distributed in prefetched data path logic, circuit, and method of ordering prefetched data
10/17/2002US20020149596 Checkerboard buffer using more than two memory devices
10/17/2002US20020149403 Semiconductor device and method of outputting data therein
10/17/2002US20020149399 High speed low power input buffer
10/17/2002US20020149397 High-speed, low- power inter-chip transmission system
10/17/2002DE10117614A1 Verfahren zum Betreiben eines Halbleiterspeichers mit doppelter Datenübertragungsrate A method of operating a semiconductor memory device with double data rate
10/17/2002DE10116914A1 Schaltungsanordnung mit einem Speicherfeld Circuit arrangement with a memory array
10/17/2002DE10116325A1 Circuit for memory, especially DRAM, has read amplifier that actively places second bit line adjacent to first bit line at defined potential while first bit line is being read out.
10/17/2002DE10115291C1 Dynamic semiconductor memory in personal computer, includes controller which is programmed to refresh memory bank by resetting all word lines and to activate word lines
10/17/2002DE10114611A1 Integrierte Logikschaltung Integrated logic circuit
10/16/2002EP1249760A1 Multi processor data processing device
10/16/2002EP1249010A1 Microprocessor system with encoding
10/16/2002EP0902436B1 Microcomputer with flash memory programmable via external terminal
10/16/2002CN1374660A Semi-conductor equipment with efficient information exchange circuit
10/16/2002CN1374659A Device and method of reducing power consumption of one-sided SRAM
10/15/2002US6467043 Adjusting and measuring the timing of a data strobe signal with a first delay line and through additional delay line adapted to receive pulse signal
10/15/2002US6467017 Programmable logic device having embedded dual-port random access memory configurable as single-port memory
10/15/2002US6467016 Apparatus to record digital data on non-volatile memory card for recording in units of blocks of digital data and method thereof
10/15/2002US6466511 Semiconductor memory having double data rate transfer technique
10/15/2002US6466508 Semiconductor memory device having high-speed read function
10/15/2002US6466505 Flexible input structure for an embedded memory
10/15/2002US6466504 Compilable block clear mechanism on per I/O basis for high-speed memory
10/15/2002US6466502 Semiconductor memory device having switching and memory cell transistors with the memory cell having the lower threshold voltage
10/15/2002US6466501 Semiconductor memory device having sense amplifier and method for driving sense amplifier
10/15/2002US6466500 Amplifier circuit
10/15/2002US6466499 DRAM sense amplifier having pre-charged transistor body nodes
10/15/2002US6466498 Discontinuity-based memory cell sensing
10/15/2002US6466497 Secondary precharge mechanism for high speed multi-ported register files
10/15/2002US6466492 Synchronous semiconductor memory device and method for controlling mask data input circuit
10/15/2002US6466491 Memory system and memory controller with reliable data latch operation
10/15/2002US6466488 Reduction of data dependent power supply noise when sensing the state of a memory cell
10/15/2002US6466487 Semiconductor device with impedance controllable output buffer
10/15/2002US6466486 Buffer circuit, and semiconductor device and semiconductor memory device including same
10/15/2002US6466470 Circuitry and method for resetting memory without a write cycle
10/15/2002US6466075 Clock signal generator for generating signal with differing phase for an integrated circuit
10/15/2002US6466059 Sense amplifier for low voltage memories
10/15/2002US6466054 Level converter circuit
10/10/2002WO2000074054A3 Semiconductor memory card, apparatus for recording data onto the semiconductor memory card, and apparatus for reproducing data of the semiconductor memory card
10/10/2002US20020147884 Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM
10/10/2002US20020147883 System and method for increasing the speed of memories
10/10/2002US20020147877 Synchronous memory device
10/10/2002US20020146025 Arbiter device for multi-port memory and semiconductor device
10/10/2002US20020145936 Semiconductor memory device with single clock signal line
10/10/2002US20020145935 Semiconductor integrated circuit
10/10/2002US20020145934 Method and apparatus for high-speed read operation in semiconductor memory
10/10/2002US20020145932 Self-timed activation logic for memory
10/10/2002US20020145931 Method and apparatus for storing data in an integrated circuit
10/10/2002US20020145930 Semiconductor integrated circuit
10/10/2002US20020145929 Control circuit and semiconductor memory device
10/10/2002US20020145928 Sense amplifier having integrated y multiplexor and method therefor
10/10/2002US20020145927 Semiconductor integrated circuit device and data-write method thereof
10/10/2002US20020145926 Integrated clock generator, particularly for driving a semiconductor memory with a test signal
10/10/2002US20020145924 System, method, and article of manufacture for using a replaceable component to select a replaceable quality of service capable network communication channel component
10/10/2002US20020145923 Circuit configuration with a memory array
10/10/2002US20020145920 Semiconductor memory device
10/10/2002US20020145918 Architecture and scheme for a non-strobed read sequence
10/10/2002US20020145917 Device and method for using complementary bits in a memory array
10/10/2002US20020145911 Method for programming a reference cell
10/10/2002US20020145900 Low power memory module using restricted RAM activation
10/10/2002US20020145452 Differential sensing amplifier for content addressable memory
10/10/2002DE10115817A1 Integrierter Speicherchip mit einem dynamischen Speicher Built-in memory chip with a dynamic memory
10/10/2002DE10115816A1 Integrierter dynamischer Speicher und Verfahren zum Betrieb eines integrierten dynamischen Speichers Integrated dynamic memory and method of operating a dynamic memory integrated
10/09/2002EP1248267A2 Semiconductor memory device and information processing system
10/09/2002EP1248266A2 Control circuit and semiconductor memory device
10/09/2002EP1248263A1 Method for programming a reference cell
10/09/2002EP1248262A1 Method for writing data into a semiconductor memory device and semiconductor memory therefor
10/09/2002EP1248261A2 Random and rapid DRAM memory access management method
10/09/2002EP1248260A1 Architecture and scheme for a non-strobed read sequence
10/09/2002EP1247234A1 A data retail system
10/09/2002EP0946542B1 Indane or dihydroindole derivatives
10/09/2002CN1373890A Circuit and method for multiple match detection in content addressable memories
10/09/2002CN1092385C Semiconductor memory device for block access applications
10/08/2002US6463558 Semiconductor memory device
10/08/2002US6463544 Method for powering down unused configuration bits to minimize power consumption
10/08/2002US6463008 Semiconductor integrated circuit device
10/08/2002US6463007 Synchronous semiconductor memory device
10/08/2002US6463006 Semiconductor integrated circuit
10/08/2002US6463005 Semiconductor memory device
10/08/2002US6463003 Power saving scheme for burst mode implementation during reading of data from a memory device
10/08/2002US6463000 First-in first-out memory device and method of generating flag signal in the same
10/08/2002US6462999 Semiconductor memory device having internal data read circuit excellent in noise immunity
10/08/2002US6462998 Programmable and electrically configurable latch timing circuit
10/08/2002US6462997 Circuit for resetting a pair of data buses of a semiconductor memory device
10/08/2002US6462996 Semiconductor integrated circuit device having internal synchronizing circuit responsive to test mode signal
10/08/2002US6462993 Semiconductor integrated circuit
10/08/2002US6462989 Technique for locally reducing effects on an analog signal due to changes on a reference bus in an integrated circuit
10/08/2002US6462987 Direct-comparison reading circuit for a nonvolatile memory array
10/08/2002US6462985 Non-volatile semiconductor memory for storing initially-setting data
10/08/2002US6462601 Electrostatic discharge protection circuit layout
10/08/2002US6462591 Semiconductor memory device having a controlled output driver characteristic
10/08/2002US6462584 Generating a tail current for a differential transistor pair using a capacitive device to project a current flowing through a current source device onto a node having a different voltage than the current source device
10/03/2002WO2002078008A2 Independent asynchronous boot block for synchronous non-volatile memory devices
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