Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
07/2002
07/30/2002US6426656 High speed, low-power inter-chip transmission system
07/25/2002US20020099988 Circuit for reading non-volatile memories
07/25/2002US20020099987 Method for guaranteeing a minimum data strobe valid window and a minimum data valid window for DDR memory devices
07/25/2002US20020099903 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
07/25/2002US20020099896 Integrated circuit device having double data rate capability
07/25/2002US20020099888 I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
07/25/2002US20020097804 Method and apparatus for data transmission
07/25/2002US20020097629 Semiconductor memory device comprising more than two internal banks of different sizes
07/25/2002US20020097624 Refresh control circuit for low-power sram applications
07/25/2002US20020097623 Semiconductor integration circuit device
07/25/2002US20020097622 Semiconductor memory and method of operating the same
07/25/2002US20020097620 Integrated memory having a cell array and charge equalization devices, and method for the accelerated writing of a datum to the integrated memory
07/25/2002US20020097614 Semiconductor memory device having sensing power driver
07/25/2002US20020097609 Semiconductor storage apparatus
07/25/2002US20020097604 Semiconductor memory device having faulty cells
07/25/2002US20020097603 Nonvolatile semiconductor memory device
07/25/2002US20020097597 MRAM bit line word line architecture
07/25/2002US20020097074 Synchronous semiconductor device for adjusting phase offset in a delay locked loop
07/25/2002US20020097071 Output buffer with constant switching current
07/25/2002US20020096679 Display driver IC
07/25/2002DE10152027A1 Synchroner Hochgeschwindigkeits-Halbleiterspeicher mit einer Vielstufen-Pipeline-Struktur und Betriebsverfahren Synchronous high-speed semiconductor memory having a multi-stage pipeline structure and method of operation
07/25/2002DE10101553C1 Halbleiterspeicher mit Verzögerungsregelkreis Semiconductor memory with delay locked loop
07/24/2002EP1225597A1 Synchronous-reading nonvolatile memory
07/24/2002EP1225595A1 Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell
07/24/2002EP1225590A2 Burst access memory system
07/24/2002EP1225589A2 Semiconductor memory device having a plurality of low power consumption modes
07/24/2002EP1225588A2 Method and circuit for determining sense amplifier sensitivity
07/24/2002EP1225587A2 Reading memory cells
07/24/2002EP1224667A1 Configurable synchronizer for double data rate synchronous dynamic random access memory
07/24/2002EP0925551B1 Method for tuning an oscillating receiver circuit of a transponder built into a rfid system
07/24/2002CN2502369Y Speech guide sightseeing tour device
07/24/2002CN1360314A Multiport memory based on dynamic random access memory core
07/23/2002US6425066 Integrated circuit comprising at least two memories
07/23/2002US6425062 Controlling burst sequence in synchronous memories
07/23/2002US6425018 Portable music player
07/23/2002US6424594 Method and apparatus for multiple latency synchronous dynamic random access memory
07/23/2002US6424593 Semiconductor memory device capable of adjusting internal parameter
07/23/2002US6424592 Semiconductor integrated circuit having circuit for correcting data output timing
07/23/2002US6424590 Semiconductor device
07/23/2002US6424580 Memory with an optimized setting of precharge times
07/23/2002US6424577 Sense amplifier circuit for use in a semiconductor memory device
07/23/2002US6424576 Apparatus and methods for selectively disabling outputs in integrated circuit devices
07/23/2002US6424575 Synchronous output buffer, particularly for non-volatile memories
07/23/2002US6424559 Method and apparatus for sense amplification
07/23/2002US6424554 Semiconductor memory with multistage local sense amplifier
07/23/2002US6424199 Semiconductor device using complementary clock and signal input state detection circuit used for the same
07/23/2002US6424198 Memory clock generation with configurable phase advance and delay capability
07/23/2002US6424181 High-speed low-power sense amplifying half-latch and apparatus thereof for small-swing differential logic (SSDL)
07/23/2002US6423584 method for forming capacitors and field effect transistors in a semiconductor integrated circuit device
07/18/2002WO2002042888A3 Device for storing and reproducing audio and/or video
07/18/2002US20020095560 Apparatus and method for pipelined memory operations
07/18/2002US20020095395 System and method of discovering information
07/18/2002US20020094626 Semiconductor memory device and write driving thereof
07/18/2002US20020093886 Reproduction method, reproduction device, editing method and editing device
07/18/2002US20020093873 Semiconductor memory device
07/18/2002US20020093871 Synchronous memory devices with synchronized latency control circuits and methods of operating same
07/18/2002US20020093870 Semiconductor memory device
07/18/2002US20020093869 Apparatus and method for operation of multi-bank semiconductor memory device with an up/down counter
07/18/2002US20020093866 Device and method for reducing standby current in a memory device by disconnecting bit line load devices in unused columns of the memory device from a supply voltage
07/18/2002US20020093864 Low-power semiconductor memory device
07/18/2002US20020093863 Circuit and method for testing a memory device
07/18/2002US20020093857 System and method for managing information objects
07/18/2002US20020093855 Semiconductor memory having a delay locked loop
07/18/2002US20020093852 Memory device
07/18/2002US20020093844 Read/write eight-slot cam with interleaving
07/18/2002US20020093068 Magnetoelectronic memory element with inductively coupled write wires
07/18/2002US20020093032 Semiconductor device
07/18/2002DE10154879A1 Semiconductor memory device e.g. DRAM has MOS transistor which shares source region of bitline isolation transistors
07/18/2002DE10141994A1 Halbleiterspeichervorrichtung zur Reduktion der Prüfzeitperiode A semiconductor memory device for reducing the Prüfzeitperiode
07/17/2002EP1223583A2 High-speed cycle clock-synchronous memory device
07/17/2002EP1222689A2 Dram bit lines and support circuitry contacting scheme
07/17/2002EP0931288B1 Layout for a semiconductor memory device having redundant elements
07/17/2002CN1359107A 数据再生装置 Data reproducing means
07/16/2002US6421297 Data-pattern-dependent compensation technique to maintain drive strength of an output driver
07/16/2002US6421294 Semiconductor memory device having large data I/O width and capable of speeding up data input/output and reducing power consumption
07/16/2002US6421292 Semiconductor memory, and memory access method
07/16/2002US6421291 Semiconductor memory device having high data input/output frequency and capable of efficiently testing circuit associated with data input/output
07/16/2002US6421290 Output circuit for alternating multiple bit line per column memory architecture
07/16/2002US6421289 Method and apparatus for charge-transfer pre-sensing
07/16/2002US6421284 Semiconductor device
07/16/2002US6421280 Method and circuit for loading data and reading data
07/16/2002US6421274 Semiconductor memory device and reading and writing method thereof
07/16/2002US6420910 Quasi-current sensing input impedance controlled preamplifier for magnetoresistive elements
07/16/2002US6420908 Sense amplifier
07/16/2002US6420754 Semiconductor integrated circuit device
07/11/2002WO2002054409A2 Bitline twist with equalizer function
07/11/2002WO2002054406A2 Method and device for operating a ram memory
07/11/2002WO2002054405A2 Memory architecture with controllable bitline lengths
07/11/2002US20020091948 Apparatus and method for improving resolution of a current mode driver
07/11/2002US20020091890 Synchronous memory device having automatic precharge
07/11/2002US20020090097 Audio signal reproducing apparatus
07/11/2002US20020089891 Random access memory with divided memory banks and data read/write architecture therefor
07/11/2002US20020089888 Sense amplifier control circuit of semiconductor memory device
07/11/2002US20020089884 Random access memory with hidden bits
07/11/2002US20020089883 Control device for a vehicle engine
07/11/2002US20020089882 Simple method of allowing random access to rambus direct dram for short burst of data
07/11/2002US20020089881 High speed semiconductor memory device with short word line switching time
07/11/2002US20020089880 Circuits and methods for inputting multi-level data through a single input/output pin
07/11/2002US20020089879 Semiconductor memory device of low power consumption
07/11/2002US20020089872 Dram array interchangeable between single-cell and twin-cell array operation