| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 06/11/2002 | US6404699 Integrated circuit having a command decoder |
| 06/11/2002 | US6404697 Data output device for synchronous memory device |
| 06/11/2002 | US6404696 Random access memory with divided memory banks and data read/write architecture therefor |
| 06/11/2002 | US6404693 Integrated circuit memory devices that select sub-array blocks and input/output line pairs based on input/output bandwidth, and methods of controlling same |
| 06/11/2002 | US6404692 Semiconductor memory |
| 06/11/2002 | US6404691 Semiconductor memory device for simple cache system |
| 06/11/2002 | US6404689 Method and structure for hiding a refresh operation in a DRAM having an interlocked pipeline |
| 06/11/2002 | US6404688 Semiconductor memory device having a self-refresh operation |
| 06/11/2002 | US6404687 Semiconductor integrated circuit having a self-refresh function |
| 06/11/2002 | US6404686 High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus |
| 06/11/2002 | US6404684 Test interface circuit and semiconductor integrated circuit device including the same |
| 06/11/2002 | US6404678 Source and drain sensing |
| 06/11/2002 | US6404677 Semiconductor memory device capable of performing stable read operation and read method thereof |
| 06/11/2002 | US6404670 Multiple ports memory-cell structure |
| 06/11/2002 | US6404664 Twisted bit line structure and method for making same |
| 06/11/2002 | US6404663 Semiconductor integrated circuit having testing mode for modifying operation timing |
| 06/11/2002 | US6404036 Semiconductor memory device with a triple well structure |
| 06/11/2002 | US6404019 Sense amplifier |
| 06/11/2002 | US6403448 Semiconductor devices having cooperative mode option at assembly stage and method thereof |
| 06/06/2002 | WO2002045094A2 Method and apparatus for built-in self-repair of memory storage arrays |
| 06/06/2002 | WO2002045050A1 A display device |
| 06/06/2002 | WO2001095334A3 Power saving scheme for burst mode implementation during reading of data from a memory device |
| 06/06/2002 | US20020067655 Control and timing structure for a memory |
| 06/06/2002 | US20020067654 Synchronous memory modules and memory systems with selectable clock termination |
| 06/06/2002 | US20020067653 Semiconductor memory having an overlaid bus structure |
| 06/06/2002 | US20020067650 Semiconductor memory with built-in cache |
| 06/06/2002 | US20020067649 Semiconductor memory, and memory access method |
| 06/06/2002 | US20020067648 Asynchronous SRAM compatible memory device using DRAM cell and method for driving the same |
| 06/06/2002 | US20020067647 Semiconductor integrated circuit device |
| 06/06/2002 | US20020067643 Reduced power bit line selection in memory circuits |
| 06/06/2002 | US20020067642 Semiconductor memory |
| 06/06/2002 | US20020067640 Semiconductor memory architecture |
| 06/06/2002 | US20020067638 Semiconductor device and data processing system |
| 06/06/2002 | US20020067635 Wide databus architecture |
| 06/06/2002 | US20020067197 Phase adjustor for semiconductor integrated circuit |
| 06/06/2002 | US20020067194 Generation of clock signals for a semiconductor memory that are edge-synchronous with the output signals of a clock generator |
| 06/06/2002 | US20020067192 Integrated circuit having a synchronous and an asynchronous circuit and method for operating such an integrated circuit |
| 06/06/2002 | DE10103991C1 Temperature detection method for semiconductor component uses evaluation of replacement voltage of memory cell transistor |
| 06/06/2002 | CA2430342A1 A display device |
| 06/05/2002 | EP1211731A2 A symmetric architecture for memory cells having widely spread metal bit lines |
| 06/05/2002 | EP1029326A4 Programmable access protection in a flash memory device |
| 06/04/2002 | US6401213 Timing circuit for high speed memory |
| 06/04/2002 | US6401180 Bank history table for improved pre-charge scheduling of random access memory banks |
| 06/04/2002 | US6401167 High performance cost optimized memory |
| 06/04/2002 | US6400641 Delay-locked loop with binary-coupled capacitor |
| 06/04/2002 | US6400635 Memory circuitry for programmable logic integrated circuit devices |
| 06/04/2002 | US6400633 Power-saving modes for memories |
| 06/04/2002 | US6400630 Circuit configuration having a variable number of data outputs and device for reading out data from the circuit configuration with the variable number of data outputs |
| 06/04/2002 | US6400629 System and method for early write to memory by holding bitline at fixed potential |
| 06/04/2002 | US6400628 Semiconductor memory device |
| 06/04/2002 | US6400627 Sensing circuit for magnetic memory unit |
| 06/04/2002 | US6400626 Memory devices |
| 06/04/2002 | US6400623 Semiconductor memory having parallel test mode |
| 06/04/2002 | US6400617 Semiconductor memory circuit having selective redundant memory cells |
| 06/04/2002 | US6400616 Method of an apparatus for correctly transmitting signals at high speed without waveform distortion |
| 06/04/2002 | US6400614 Transmission device and integrated circuit |
| 06/04/2002 | US6400613 Positive write masking method and apparatus |
| 06/04/2002 | US6400611 Independent asynchronous boot block for synchronous non-volatile memory devices |
| 06/04/2002 | US6400609 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein |
| 06/04/2002 | US6400597 Semiconductor memory device |
| 06/04/2002 | US6400208 On-chip trim link sensing and latching circuit for fuse links |
| 06/04/2002 | US6400202 Programmable delay element and synchronous DRAM using the same |
| 06/04/2002 | US6400186 Settable digital CMOS differential sense amplifier |
| 06/04/2002 | US6399975 Wide bit memory using post passivation interconnection scheme |
| 05/30/2002 | WO2002043070A1 A method for non-destructive readout and apparatus for use with the method |
| 05/30/2002 | WO2002043069A2 Boundary addressable memory |
| 05/30/2002 | WO2002042888A2 Device for storing and reproducing audio and/or video |
| 05/30/2002 | WO2002005281A3 A high speed dram architecture with uniform access latency |
| 05/30/2002 | WO2002003459A3 High-speed low-power semiconductor memory architecture |
| 05/30/2002 | WO2001097373A3 Multiple output current mirror with improved accuracy |
| 05/30/2002 | WO2001075898A3 Interface command architecture for synchronous flash memory |
| 05/30/2002 | WO2001075897A3 Synchronous flash memory |
| 05/30/2002 | US20020066047 Memory controller with temperature sensors |
| 05/30/2002 | US20020066001 Adaptive calibration technique for high speed memory devices |
| 05/30/2002 | US20020065997 Multi-port memory device and system for addressing the multi-port memory device |
| 05/30/2002 | US20020064083 Clock generating circuits controlling activation of a delay locked loop circuit on transition to a standby mode of a semiconductor memory device and methods for operating the same |
| 05/30/2002 | US20020064082 Semiconductor integrated circuit having circuit for correcting data output timing |
| 05/30/2002 | US20020064080 Semiconductor memory device |
| 05/30/2002 | US20020064079 Semiconductor memory device having a plurality of low power consumption modes |
| 05/30/2002 | US20020064077 Semiconductor device including internal potential generating circuit allowing tuning in short period of time and reduction of chip area |
| 05/30/2002 | US20020064075 Semiconductor memory device with reduced interference between bit lines |
| 05/30/2002 | US20020064072 Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode |
| 05/30/2002 | US20020063595 Circuit configuration with internal supply voltage |
| 05/30/2002 | US20020063335 Semiconductor integrated circuit with dummy patterns |
| 05/29/2002 | EP1209686A2 An improved integrated circuit memory device having interleaved read and program capabilities and methods of operating same |
| 05/29/2002 | EP1208567A1 Double data rate scheme for data output |
| 05/29/2002 | EP1002369B1 Synchronous clock generator including delay-locked loop |
| 05/29/2002 | EP0795152B1 Adaptive dram timing |
| 05/29/2002 | DE10136503A1 Sense amplifier integrated circuit for high speed semiconductor memory, has current amplifier with input stage and output stage which are responsive to control signal that reduces gain of current amplifier |
| 05/29/2002 | DE10133595A1 Pufferschaltung, Speicherzugriffsverfahren, Speicherbauelement und Reed-Solomon-Decoder Buffer circuit, memory access method, memory device and Reed-Solomon decoder |
| 05/29/2002 | DE10121708A1 Halbleiterspeichereinrichtung und Verfahren zum Ändern von Ausgangsdaten dieser Einrichtung Semiconductor memory device and method of changing output data of this institution |
| 05/29/2002 | DE10055709A1 Data processing unit has arrangements for converting digital signals to analog and transferring to sound head of external cassette recorder housing similar to conventional music cassette housing |
| 05/29/2002 | CN2493993Y Digital recording language learning apparatus |
| 05/29/2002 | CN1351350A Method for partitioning memory block and identifying R/W information in flash memory |
| 05/28/2002 | US6396768 Synchronous semiconductor memory device allowing easy and fast test |
| 05/28/2002 | US6396765 Semiconductor memory having an overlaid bus structure |
| 05/28/2002 | US6396764 Segmented memory architecture and systems and methods using the same |
| 05/28/2002 | US6396759 Semiconductor device with test fuse links, and method of using the test fuse links |
| 05/28/2002 | US6396757 Multiple output current mirror with improved accuracy |
| 05/28/2002 | US6396747 Semiconductor memory device capable of high speed input/output of wide bandwidth data by improving usage efficiency of external data bus |