Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
11/2002
11/27/2002EP1260899A2 Circuit and method for generating a delayed internal clock signal
11/27/2002EP1259963A1 Memory device with support for unaligned access
11/27/2002EP1016086B1 Method and apparatus for adjusting the timing of signals over fine and coarse ranges
11/27/2002EP0870241B1 Protocol for communication with dynamic memory
11/27/2002CN1382295A 存储装置 Storage device
11/27/2002CN1381847A 半导体存储器装置 The semiconductor memory device
11/27/2002CN1095130C Adjustable depth/width FIFO buffer for width changeable data transfer
11/27/2002CN1095123C 半导体装置 Semiconductor device
11/26/2002US6487629 Semiconductor memory for operation in a plurality of operational modes
11/26/2002US6487212 Queuing structure and method for prioritization of frames in a network switch
11/26/2002US6487142 Synchronous dynamic random access memory
11/26/2002US6487141 Digital delay, digital phase shifter
11/26/2002US6487140 Circuit for managing the transfer of data streams from a plurality of sources within a system
11/26/2002US6487137 Semiconductor memory device having a second voltage supplier supplying transfer gates with a second voltage higher than a first voltage
11/26/2002US6487135 Semiconductor device
11/26/2002US6487134 Single-event upset tolerant latch for sense amplifiers
11/26/2002US6487133 Semiconductor device
11/26/2002US6487132 Integrated circuit memory devices having multiple input/output buses and precharge circuitry for precharging the input/output buses between write operations
11/26/2002US6487130 Semiconductor integrated circuit device
11/26/2002US6487128 Integrated memory having memory cells and reference cells, and operating method for such a memory
11/26/2002US6487127 Circuit configuration for reading and writing information at a memory cell field
11/26/2002US6487123 Semiconductor integrated circuit, ink cartridge having the semiconductor integrated circuit, and inkjet recording device having the ink cartridge attached
11/26/2002US6487122 Multi-value semiconductor memory device with write verify circuit
11/26/2002US6486885 Memory device and method
11/26/2002US6486713 Differential input buffer with auxiliary bias pulser circuit
11/26/2002US6486651 Integrated circuit devices having a delay locked loop that is configurable for high-frequency operation during test and methods of operating same
11/21/2002WO2002093744A1 Apparatus/method for distributing a clock signal
11/21/2002WO2002093582A1 Propagation delay independent sdram data capture device and method
11/21/2002US20020174291 High speed embedded dram with sram-like interface
11/21/2002US20020174289 Method and apparatus to enhance testability and validation of memory
11/21/2002US20020174287 Portable data storage device capable of being directly connected via USB plug to a computer
11/21/2002US20020174274 DDR and QDR converter and interface card, motherboard and memory module interface using the same
11/21/2002US20020173866 Digital mp3 audio device
11/21/2002US20020172304 Clock recovery circuit and receiver circuit for improving the error rate of signal reproduction
11/21/2002US20020172090 SDRAM having data latch circuit for outputting input data in synchronization with a plurality of control signals
11/21/2002US20020172088 Supply noise reduction in memory device column selection
11/21/2002US20020172087 Address control apparatus of semiconductor memory device using bank address
11/21/2002US20020172085 Integrated memory
11/21/2002US20020172080 Propagation delay independent sdram data capture device and method
11/21/2002US20020172078 Semiconductor memory device
11/21/2002US20020172076 Sensing scheme for low-voltage flash memory
11/21/2002US20020171463 Minimizing the effect of clock skew in bit line write driver
11/21/2002US20020171453 Differential amplifier circuit capable of accurately amplifying even high-speeded signal of small amplitude
11/21/2002US20020171437 Semiconductor memory device having noise tolerant input buffer
11/20/2002EP1258005A1 Hand-held audio decoder
11/20/2002EP1257929A1 Sound and image producing system
11/20/2002CN1380793A Equipment for procesing data by means of multi processor
11/20/2002CN1380746A Semiconductor memory with single clock signal line
11/20/2002CN1380698A Method and device for high-speed read operation in semiconductor memory
11/20/2002CN1380695A Semiconductor IC device and design method thereof
11/20/2002CN1380660A 控制电路和半导体存储器装置 The control circuit and semiconductor memory device
11/20/2002CN1380658A Method for writing-in action by using source bias to excute non-volatility internal storage unit
11/20/2002CN1380607A Memory and circuit for ordering its prefetched data and its method
11/19/2002US6484277 Integrated memory having a redundancy function
11/19/2002US6484268 Signal transmission system having a timing adjustment circuit
11/19/2002US6484246 High-speed random access semiconductor memory device
11/19/2002US6484244 Method and system for storing and processing multiple memory commands
11/19/2002US6484232 Adaptive calibration technique for high speed memory devices
11/19/2002US6484231 Synchronous SRAM circuit
11/19/2002US6483772 Semiconductor memory device capable of masking data to be written
11/19/2002US6483771 Semiconductor memory device and method of operation having delay pulse generation
11/19/2002US6483770 Synchronous semiconductor memory device and method for operating same
11/19/2002US6483769 SDRAM having posted CAS function of JEDEC standard
11/19/2002US6483768 Current driver configuration for MRAM
11/19/2002US6483767 Method of constructing a very wide, very fast distributed memory
11/19/2002US6483766 Interface circuit for using in high-speed semiconductor device and interfacing method
11/19/2002US6483765 Semiconductor memory device and bit line connecting method thereof
11/19/2002US6483763 Semiconductor memory device
11/19/2002US6483762 tRCD margin
11/19/2002US6483761 Semiconductor memory device
11/19/2002US6483757 Delay-locked loop with binary-coupled capacitor
11/19/2002US6483754 Self-time scheme to reduce cycle time for memories
11/19/2002US6483753 Endianess independent memory interface
11/19/2002US6483748 Nonvolatile memory with background operation function
11/19/2002US6483579 Clock synchronization semiconductor memory device
11/19/2002US6483448 System and method for reducing timing mismatch in sample and hold circuits using an FFT and decimation
11/19/2002US6483373 Input circuit having signature circuits in parallel in semiconductor device
11/19/2002US6483359 Delay locked loop for use in semiconductor memory device
11/19/2002US6483353 Current sense amplifier circuits containing latches for improving stability and amplification in semiconductor devices
11/19/2002US6483352 Current mirror sense amplifier
11/19/2002US6483351 Input-output line sense amplifier having small current consumption and direct current
11/19/2002US6483350 Sense-amplifying circuit
11/19/2002US6483347 High speed digital signal buffer and method
11/14/2002WO2002091190A2 Memory with a bit line block and/or a word line block for preventing reverse engineering
11/14/2002US20020170014 Apparatus and method to facilitate self-correcting memory
11/14/2002US20020169933 Scalble memory
11/14/2002US20020169922 Read/write timing calibration of a memory array using a row or a redundant row
11/14/2002US20020169919 Column address path circuit and method for memory devices having a burst access mode
11/14/2002US20020169022 Method and apparatus for write protecting a gaming storage medium
11/14/2002US20020168816 That conduct successive operations by generating addresses subsequently among different operation modes; synchronous dynamic random access memory (SDRAM)
11/14/2002US20020167859 Precharge control signal generator, and semiconductor memory device using the same
11/14/2002US20020167858 Dummy wordline for controlling the timing of the firing of sense amplifiers in a memory device in relation to the firing of wordlines in the memory device
11/14/2002US20020167857 Apparatus and method for distributing a clock signal on a large scale integrated circuit
11/14/2002US20020167856 Memory system
11/14/2002US20020167854 Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operation
11/14/2002US20020167853 Semiconductor memory device
11/14/2002US20020167848 Method and circuit configuration for a memory for reducing parasitic coupling capacitances
11/14/2002US20020167838 Resistive cross point memory with on-chip sense amplifier calibration method and apparatus
11/14/2002US20020167832 Data memory
11/14/2002US20020167346 Circuits and methods for generating internal clock signal of intermediate phase relative to external clock
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