Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
10/2002
10/31/2002US20020159313 Cross-talk removal apparatus and data reproduction apparatus
10/31/2002US20020159312 Method of reading stored data and semiconductor memory device
10/31/2002US20020159309 Current saving semiconductor memory and method
10/31/2002US20020159303 Asynchronous, High-bandwidth memory component using calibrated timing elements
10/31/2002US20020159302 Data register with integrated signal level conversion
10/31/2002US20020159300 Bus driving circuit and memory device having same
10/31/2002US20020159299 Data transfer circuit and semiconductor integrated circuit having the same
10/31/2002US20020159285 Data balancing scheme in solid state storage devices
10/31/2002US20020159179 Data recording and reproducing apparatus and data reproducing apparatus
10/31/2002US20020158672 High-speed sense amplifier with auto-shutdown precharge path
10/31/2002US20020158669 Semiconductor memory device input circuit
10/31/2002US20020158275 Power down voltage control method and apparatus
10/30/2002EP1253596A2 Power down voltage control method and apparatus
10/30/2002EP1252630A2 A prefetch write driver for a random access memory
10/30/2002CN2519384Y Flash storage disc having audio frequency document display function
10/30/2002CN1377040A Semiconductor memory device and information process system
10/30/2002CN1093702C Fast progapation technique in CMOS integrated circuits
10/29/2002US6473468 Data transmission device
10/29/2002US6473360 Synchronous semiconductor memory device capable of high speed reading and writing
10/29/2002US6473358 Semiconductor memory device
10/29/2002US6473356 Low power read circuitry for a memory circuit based on charge redistribution between bitlines and sense amplifier
10/29/2002US6473352 Semiconductor integrated circuit device having efficiently arranged link program circuitry
10/29/2002US6473350 Semiconductor memory device having memory cell array structure with improved bit line precharge time and method thereof
10/29/2002US6473349 Cascode sense AMP and column select circuit and method of operation
10/29/2002US6473348 Data sensing circuit of semiconductor memory
10/29/2002US6473343 Signal amplification circuit for amplifying and sensing current difference and semiconductor memory device including same
10/29/2002US6473329 Semiconductor memory and method for accessing semiconductor memory
10/29/2002US6473326 Memory structures having selectively disabled portions for power conservation
10/29/2002US6473325 Bit line sensing control circuit for a semiconductor memory device and layout of the same
10/29/2002US6473324 Layout of a sense amplifier with accelerated signal evaluation
10/29/2002US6472929 Semiconductor device
10/29/2002US6472922 System and method for flexibly distributing timing signals
10/29/2002US6472920 High speed latch circuit
10/29/2002US6471130 Information storage apparatus and information processing apparatus using the same
10/24/2002US20020157031 Capture clock generator using master and slave delay locked loops
10/24/2002US20020156967 Semiconductor memory device
10/24/2002US20020155677 Electronic device with interleaved portions for use in integrated circuits
10/24/2002US20020154721 Method and apparatus for generating a phase dependent control signal
10/24/2002US20020154566 Sending signal through integrated circuit during setup time
10/24/2002US20020154565 Method and apparatus for read operation and write operation in semiconductor memory device
10/24/2002US20020154564 Semiconductor integrated circuit device
10/24/2002US20020154563 Fuse read sequence for auto refresh power reduction
10/24/2002US20020154562 Semiconductor integrated circuit device
10/24/2002US20020154561 Sense amplifier for reduction of access device leakage
10/24/2002US20020154550 Method and apparatus for generating and controlling integrated circuit memory write signals
10/24/2002US20020154549 Bus driving circuit and memory device having same
10/24/2002US20020154548 Fully synchronous pipelined RAM
10/24/2002US20020154546 Non-volatile, electrically alterable semiconductor memory
10/24/2002US20020154541 Non-volatile memory embedded in a conventional logic process
10/24/2002US20020154534 Method and circuit for determining sense amplifier sensitivity
10/24/2002US20020153941 Semiconductor device having a pump circuit
10/24/2002US20020153936 Method and apparatus for receiving high speed signals with low latency
10/24/2002US20020153933 Semiconductor device using complementary clock and signal input state detection circuit used for the same
10/24/2002DE10201865A1 Speichervorrichtung mit einer Vorauslesedaten-Ordnung, die in einer Vorauslese-Datenpfadlogik verteilt ist, sowie Schaltung und Verfahren zum Ordnen von Vorauslesedaten Memory device having a prefetch data order, which is distributed in a prefetch data path logic, and circuit and method for arranging prefetch data
10/24/2002DE10160089A1 Halbleiterspeichervorrichtung A semiconductor memory device
10/24/2002DE10135573A1 Transistor arrangement as sense amplifier has at least one second double row of paired transistors of first or second type; rows are offset and gaps of at least one row are left
10/24/2002DE10117891A1 Integrierter Taktgenerator, insbesondere zum Ansteuern eines Halbleiterspeichers mit einem Testsignal An integrated clock generator, in particular for driving a semiconductor memory with a test signal
10/23/2002EP1251523A1 Method and circuit for timing dynamic reading of a memory cell with control of the integration time
10/23/2002EP1251522A2 Semiconductor memory device
10/23/2002EP1251521A1 A dynamic random access memory device externally functionally equivalent to a static random access memory
10/23/2002EP1251518A2 Method and apparatus for high-speed read operation in semiconductor memory
10/23/2002CN1376298A Memory devices
10/22/2002US6470439 FIFO memory control circuit
10/22/2002US6470433 Modified aggressive precharge DRAM controller
10/22/2002US6470431 Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data
10/22/2002US6470418 Pipelining a content addressable memory cell array for low-power operation
10/22/2002US6470405 Protocol for communication with dynamic memory
10/22/2002US6470402 Increasing values of a read and a trigger pointers when a write pointer reaches the read pointer in a circular FIFO (first-in-first-out) store
10/22/2002US6470304 Method and apparatus for eliminating bitline voltage offsets in memory devices
10/22/2002US6470060 Method and apparatus for generating a phase dependent control signal
10/22/2002US6469955 Integrated circuit memory device having interleaved read and program capabilities and methods of operating same
10/22/2002US6469954 Device and method for reducing idle cycles in a semiconductor memory device
10/22/2002US6469951 Semiconductor memory having an overlaid bus structure
10/22/2002US6469950 Static memory cell having independent data holding voltage
10/22/2002US6469948 Semiconductor device
10/22/2002US6469945 Dynamically configurated storage array with improved data access
10/22/2002US6469944 Method of compensating for a defect within a semiconductor device
10/22/2002US6469940 Memory access method and system for writing and reading SDRAM
10/22/2002US6469937 Current sense amplifier circuit
10/22/2002US6469929 Structure and method for high speed sensing of memory arrays
10/22/2002US6469573 Semiconductor integrated circuit
10/22/2002US6469566 Pre-charging circuit of an output buffer
10/22/2002US6469555 Apparatus and method for generating multiple clock signals from a single loop circuit
10/22/2002US6469546 Sense amplifier circuit
10/22/2002US6469539 Impedance controlled output circuit having multi-stage of high code selectors in semiconductor device and method for operating the same
10/17/2002WO2002082460A1 Semiconductor non-volatile storage device
10/17/2002WO2002082456A1 Device and method for using complementary bits in a memory array
10/17/2002WO2002082454A1 Semiconductor storage device
10/17/2002WO2002082450A1 Method for operating a semiconductor memory at a data transmission rate which is twice as fast
10/17/2002WO2002054406A3 Method and device for operating a ram memory
10/17/2002US20020152442 Error correction code circuits
10/17/2002US20020152365 Memory device
10/17/2002US20020152351 Memory control circuit
10/17/2002US20020149993 Fast cycle RAM and data readout method therefor
10/17/2002US20020149992 Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devices
10/17/2002US20020149991 Test circuit for testing semiconductor memory
10/17/2002US20020149990 Semiconductor memory device having asymmetric data paths
10/17/2002US20020149982 Memory device tester and method for testing reduced power states
10/17/2002US20020149981 Memory device tester and method for testing reduced power states
10/17/2002US20020149973 Semiconductor memory device
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