Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
10/2002
10/03/2002WO2002078007A1 Integrated logic circuit
10/03/2002WO2002078003A2 Method and apparatus for biasing selected and unselected array lines when writing a memory array
10/03/2002WO2002078002A1 Memory device and method having data path with multiple prefetch i/o configurations
10/03/2002WO2002078001A2 Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays
10/03/2002WO2002077787A2 Method, apparatus, and system to enhance an interface of a flash memory device
10/03/2002US20020144277 Method for field-programming a solid-state memory device with a digital media file
10/03/2002US20020144210 SDRAM address error detection method and apparatus
10/03/2002US20020144206 Error correction apparatus for performing consecutive reading of multiple code words
10/03/2002US20020144051 Memory arrangement and method for reading from a memory arrangement
10/03/2002US20020141281 Memory device which samples data after an amount of time transpires
10/03/2002US20020141280 Clock synchronous type semiconductor memory device
10/03/2002US20020141275 Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies
10/03/2002US20020141272 Dynamic semiconductor memory with refresh and method for operating such a memory
10/03/2002US20020141270 Semiconductor memory device
10/03/2002US20020141266 Data input/output method
10/03/2002US20020141265 Apparatus and method for a memory storage cell leakage cancellation scheme
10/03/2002US20020141258 Semiconductor device
10/03/2002US20020141253 Selective forwarding of a strobe based on a predetermined delay following a memory read command
10/03/2002US20020141252 Semiconductor memory having mirroring function
10/03/2002US20020141251 Method and circuit for processing output data in pipelined circuits
10/03/2002US20020141246 Output buffer capable of adjusting current drivability and semiconductor integrated circuit device having the same
10/03/2002US20020141245 Semiconductor memory device
10/03/2002US20020141230 Integrated memory chip with a dynamic memory
10/03/2002US20020141229 Integrated dynamic memory device and method for operating an integrated dynamic memory
10/03/2002US20020141228 Low power consumption semiconductor memory
10/03/2002US20020141226 Semiconductor memory device and control method thereof
10/03/2002US20020141225 Semiconductor memory and method for accessing semiconductor memory
10/03/2002US20020141219 System and method for reducing noise of congested datalines in an edram
10/03/2002US20020140493 CMOS output circuit
10/03/2002US20020140480 Sense amplifier flip-flop
10/03/2002US20020140473 Apparatus and method for generating clock signals
10/03/2002US20020140471 Pre-divider architecture for low power in a digital delay locked loop
10/03/2002US20020140016 Magnetic random access memory having a transistor of vertical structure and the method thereof
10/03/2002US20020140015 System with meshed power and signal buses on cell array
10/03/2002CA2441898A1 Independent asynchronous boot block for synchronous non-volatile memory devices
10/02/2002EP1246388A2 Clock recovery circuit and receiver circuit
10/02/2002EP1246194A2 Semiconductor memory device
10/02/2002EP1245030A1 Memory device
10/02/2002EP0943177B1 Clock vernier adjustment
10/02/2002DE10114159A1 Verfahren und Vorrichtung zur Datenübertragung Method and apparatus for data transmission
10/02/2002CN1372268A Read amplifier control circuit for semiconductor storage device
10/02/2002CN1372267A Method and device for controlling interdependent sequence in multi-quene structure
10/02/2002CN1372266A Machine processing beared memory with time division recharge structure
10/02/2002CN1372202A Semiconductor storage device and information process unit
10/02/2002CN1091925C 存储器设备 Memory device
10/01/2002US6460121 Method for providing an atomic memory read using a compare-exchange instruction primitive
10/01/2002US6459652 Semiconductor memory device having echo clock path
10/01/2002US6459651 Semiconductor memory device having data masking pin and memory system including the same
10/01/2002US6459647 Split-bank architecture for high performance SDRAMs
10/01/2002US6459641 Semiconductor memory device
10/01/2002US6459639 Semiconductor memory device
10/01/2002US6459637 Zero margin enable controlling apparatus and method of sense amplifier adapted to semiconductor memory device
10/01/2002US6459636 Mode selection circuit for semiconductor memory device
10/01/2002US6459635 Apparatus and method for increasing test flexibility of a memory device
10/01/2002US6459632 Semiconductor memory device having redundancy function
10/01/2002US6459629 Memory with a bit line block and/or a word line block for preventing reverse engineering
10/01/2002US6459627 Semiconductor memory device
10/01/2002US6459626 Integrated memory having memory cells and reference cells, and corresponding operating method
10/01/2002US6459617 Method and circuitry for bank tracking in write command sequence
10/01/2002US6459320 Impedance matching circuit for semiconductor memory device
10/01/2002US6459317 Sense amplifier flip-flop
10/01/2002US6459307 Input buffer having dual paths
10/01/2002US6459119 Contact array structure for buried type transistor
10/01/2002US6458644 Data bus architecture for integrated circuit devices having embedded dynamic random access memory (DRAM) with a large aspect ratio providing reduced capacitance and power requirements
09/2002
09/26/2002WO2002075745A1 Storage device, storage device controlling method, and program
09/26/2002US20020138815 Method for designing circuit layout of non-neighboring metal bit lines to reduce coupling effect
09/26/2002US20020138689 Memory device with receives write masking information
09/26/2002US20020138685 Look-ahead, wrap-around first-in, first-out integrated (FIFO) circuit device architecture
09/26/2002US20020138676 Method, apparatus, and system to enhance an interface of a flash memory device
09/26/2002US20020138243 Semiconductor integrated circuit device
09/26/2002US20020136243 Method and device for data transfer
09/26/2002US20020136081 Semiconductor integrated circuit device
09/26/2002US20020136079 Semiconductor memory device and information processing system
09/26/2002US20020136076 Memory device and method for sensing while programming a non-volatile memory cell
09/26/2002US20020136074 Semiconductor device
09/26/2002US20020136073 Integrated circuit devices having a sense amplifier driver disposed between one or more pairs of sense amplifiers and methods of manufacturing same
09/26/2002US20020136069 Method and device for reducing average access time of a non-volatile memory during reading
09/26/2002US20020136067 Semiconductor memory device having a hierarchical bit line architecture
09/26/2002US20020136061 Method and memory system for writing in data
09/26/2002US20020136059 Method and system for increasing programming bandwidth in a non-volatile memory device
09/26/2002US20020136057 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
09/26/2002US20020136056 Nonvolatile memory system, semiconductor memory, and writing method
09/26/2002US20020136051 Small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays
09/26/2002US20020136047 Method and apparatus for biasing selected and unselected array lines when writing a memory array
09/26/2002US20020136045 Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays
09/26/2002US20020135501 Memory device and method having data path with multiple prefetch I/O configurations
09/26/2002US20020135413 Stabilized delay circuit
09/26/2002US20020135411 Semiconductor module
09/26/2002US20020135409 Method for noise and power reduction for digital delay lines
09/26/2002US20020135397 Semiconductor integrated circuits with power reduction mechanism
09/26/2002US20020135394 Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode
09/26/2002US20020135018 Thin film magnetic memory device writing data of a plurality of bits in parallel
09/26/2002US20020134994 Memory configuration
09/26/2002DE10114443A1 Writing data involves feeding address in before data item, temporarily storing it then passing it to address decoder after delay; address and data item are almost simultaneously fed to decoder
09/26/2002DE10113821A1 Semiconducting component has hold latch for early external signal latching, decoupling hold time from startup time, full latch after logic circuit to finally latch external signal
09/26/2002DE10112281A1 Leseverstärkeranordnung für eine Halbleiterspeichereinrichtung Sense amplifier configuration for a semiconductor memory device
09/25/2002EP1244110A2 Protocol for communication with dynamic memory
09/25/2002EP1242996A1 A sdram with a maskable input
09/25/2002EP1242868A1 Organization of blocks within a nonvolatile memory unit to effectively decrease sector write operation time
09/25/2002EP1012845B1 Method and apparatus for local control signal generation in a memory device
1 ... 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 ... 532