| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 04/25/2002 | US20020049600 Speech processor apparatus and system |
| 04/25/2002 | US20020048207 Data bus sense amplifier circuit |
| 04/25/2002 | US20020048198 Diffusion replica delay circuit |
| 04/25/2002 | US20020048197 Sdram having posted cas function of jedec standard |
| 04/25/2002 | US20020048196 High-speed synchronous semiconductor memory having multi-stage pipeline structure and operating method |
| 04/25/2002 | US20020048195 High speed data bus |
| 04/25/2002 | US20020048194 High speed data bus |
| 04/25/2002 | US20020048189 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein |
| 04/25/2002 | US20020048183 High speed data bus |
| 04/25/2002 | US20020047167 Intergrated semiconductor circuit with a semiconductor memory configuration embedded in a semiconductor chip |
| 04/25/2002 | DE10051164A1 Method for masking data bits to be input into a semiconductor memory by a memory controller gives the data bits to be masked an increased voltage level. |
| 04/25/2002 | DE10050702A1 Memory module system for use as DRAM, has first and second module cards with DRAM components and ECC element to be plugged into first and second plug-in bases in a coordinated manner |
| 04/24/2002 | EP1199724A1 Simply interfaced semiconductor integrated circuit device including logic circuitry and embedded memory circuitry |
| 04/24/2002 | EP1199723A1 Interlaced memory device with random or sequential access |
| 04/24/2002 | EP1199722A2 Circuit for generating sense amplifer control signals |
| 04/24/2002 | EP1199639A2 A semiconductor memory device with a large storage capacity memory and a fast speed memory |
| 04/24/2002 | CN1346493A Integrated memory with memory cells and reference cells and corresponding operating method |
| 04/24/2002 | CN1346151A Semicondcutor IC |
| 04/24/2002 | CN1346131A Clock synchronous circuit |
| 04/24/2002 | CN1346130A Non-volatile semiconductor memory |
| 04/23/2002 | US6378102 Synchronous semiconductor memory device with multi-bank configuration |
| 04/23/2002 | US6378065 Apparatus with context switching capability |
| 04/23/2002 | US6378056 Method and apparatus for configuring a memory device and a memory channel using configuration space registers |
| 04/23/2002 | US6378032 Bank conflict avoidance in multi-bank DRAMS with shared sense amplifiers |
| 04/23/2002 | US6378020 System having double data transfer rate and intergrated circuit therefor |
| 04/23/2002 | US6378008 Output data path scheme in a memory device |
| 04/23/2002 | US6377929 Solid-state audio recording unit |
| 04/23/2002 | US6377902 Arrangement for continuous and uninterrupted reading of a large volume of data from an electronic measuring device into a memory |
| 04/23/2002 | US6377513 Method for writing data to semiconductor memory and semiconductor memory |
| 04/23/2002 | US6377512 Clock synchronous type semiconductor memory device that can switch word configuration |
| 04/23/2002 | US6377511 Semiconductor integrated circuit device |
| 04/23/2002 | US6377509 Semiconductor integrated circuit |
| 04/23/2002 | US6377506 Semiconductor device |
| 04/23/2002 | US6377503 Synchronous dynamic random access memory |
| 04/23/2002 | US6377501 Semiconductor integrated circuit device |
| 04/23/2002 | US6377495 Apparatus and method for providing a bias to read memory elements |
| 04/23/2002 | US6377492 Memory architecture for read and write at the same time using a conventional cell |
| 04/23/2002 | US6377485 Multi-value semiconductor memory device and reading method thereof |
| 04/23/2002 | US6377483 Semiconductor memory device having improved memory cell and bit line pitch |
| 04/23/2002 | US6377093 Time-to-digital converter and locking circuit and method using the same |
| 04/23/2002 | US6376869 Semiconductor device |
| 04/18/2002 | WO2002031832A2 Methods and systems for reducing heat flux in memory systems |
| 04/18/2002 | WO2002011147A3 Integrated circuit with a temperature sensor |
| 04/18/2002 | WO2002001571A3 Shielded bit line architecture for memory arrays |
| 04/18/2002 | WO2001075893A3 Symmetrical protection scheme for first and last sectors of synchronous flash memory |
| 04/18/2002 | US20020046383 Partitioned random access memory |
| 04/18/2002 | US20020046358 Memory redundancy implementation |
| 04/18/2002 | US20020046356 Integrated circuit with multiprocessor architecture |
| 04/18/2002 | US20020046331 Memory system and method for two step write operations |
| 04/18/2002 | US20020046314 Synchronous memory device having automatic precharge |
| 04/18/2002 | US20020044493 Integrated memory and corresponding operating method |
| 04/18/2002 | US20020044490 Semiconductor memory device |
| 04/18/2002 | US20020044487 Read compression in a memory |
| 04/18/2002 | US20020043997 Charge compensation control circuit and method for use with output driver |
| 04/18/2002 | US20020043996 Semiconductor device capable of generating highly precise internal clock |
| 04/18/2002 | US20020043669 Semiconductor device |
| 04/18/2002 | DE10043730C1 Verfahren und Vorrichtung zur zeitlichen Korrektur eines Datensignals Method and apparatus for time correction of a data signal |
| 04/17/2002 | EP1197869A2 Integrated circuit with multiprocessor architecture |
| 04/17/2002 | EP1197830A2 Integrated circuit I/O using a high performance bus interface |
| 04/17/2002 | EP1196923A1 Electronic system using cards, postcards, letter-cards, envelopes for mailed correspondence, flat and level objects in general |
| 04/17/2002 | EP1025644A4 A master-slave delay locked loop for accurate delay of non-periodic signals |
| 04/17/2002 | EP0744073B1 A synchronous nand dram architecture |
| 04/17/2002 | CN1345439A Driver with built-in RAM, Display unit with the driver and electronic device |
| 04/17/2002 | CN1345438A Driver with built-in RAM, display unit with the driver and electronic device |
| 04/17/2002 | CN1345070A Semiconductor storage having data masking pin and storage system including the same |
| 04/17/2002 | CN1345069A Method and device for reading memory cell of resistance crossover point array |
| 04/16/2002 | US6374393 Logic circuit evaluation using sensing latch logic |
| 04/16/2002 | US6373785 Semiconductor memory device |
| 04/16/2002 | US6373784 Semiconductor memory device |
| 04/16/2002 | US6373782 Semiconductor device with reduced error operation caused by threshold voltage variation |
| 04/16/2002 | US6373781 Priority determining circuit for non-volatile memory |
| 04/16/2002 | US6373779 Block RAM having multiple configurable write modes for use in a field programmable gate array |
| 04/16/2002 | US6373778 Burst operations in memories |
| 04/16/2002 | US6373777 Semiconductor memory |
| 04/16/2002 | US6373776 Dynamic ram and semiconductor device |
| 04/16/2002 | US6373775 Semiconductor memory device with restrained scale of decoding circuit used in shift redundancy |
| 04/16/2002 | US6373773 Semiconductor device with DRAM and logic part integrated |
| 04/16/2002 | US6373768 Apparatus and method for thermal regulation in memory subsystems |
| 04/16/2002 | US6373764 Semiconductor memory device allowing static-charge tolerance test between bit lines |
| 04/16/2002 | US6373763 Semiconductor memory provided with data-line equalizing circuit |
| 04/16/2002 | US6373761 Method and apparatus for multiple row activation in memory devices |
| 04/16/2002 | US6373753 Memory array having selected word lines driven to an internally-generated boosted voltage that is substantially independent of VDD |
| 04/16/2002 | US6373752 Synchronous dynamic random access memory device |
| 04/16/2002 | US6373751 Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies |
| 04/16/2002 | US6373746 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells |
| 04/16/2002 | US6373741 Memory circuit architecture |
| 04/16/2002 | US6373341 Voltage and temperature compensated ring oscillator frequency stabilizer |
| 04/16/2002 | US6373309 Duty cycle compensation circuit of delay locked loop for Rambus DRAM |
| 04/16/2002 | US6373307 Semiconductor integrated circuit |
| 04/16/2002 | US6373303 Sync signal generating circuit provided in semiconductor integrated circuit |
| 04/16/2002 | US6373281 Tri-state dynamic body charge modulation for sensing devices in SOI RAM applications |
| 04/11/2002 | WO2002029894A2 Sense amplifier layout |
| 04/11/2002 | WO2002029817A2 Upscaled clock feeds memory to make parallel waves |
| 04/11/2002 | WO2000072538A9 Differential receiver |
| 04/11/2002 | US20020042898 Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry |
| 04/11/2002 | US20020041649 Method and apparatus for temporally correcting a data signal |
| 04/11/2002 | US20020041535 Full page increment/decrement burst for DDR SDRAM/SGRAM |
| 04/11/2002 | US20020041532 Semiconductor memory device having high data input/output frequency and capable of efficiently testing circuit associated with data input/output |
| 04/11/2002 | US20020041523 High speed data bus |
| 04/11/2002 | US20020041522 High speed data bus |