| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 08/27/2002 | US6442099 Low power read scheme for memory array structures |
| 08/27/2002 | US6442098 High performance multi-bank compact synchronous DRAM architecture |
| 08/27/2002 | US6442097 Virtual channel DRAM |
| 08/27/2002 | US6442096 Fast accessing of a memory device |
| 08/27/2002 | US6442095 Semiconductor memory device with normal mode and power down mode |
| 08/27/2002 | US6442094 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array |
| 08/27/2002 | US6442093 Cascode barrel read |
| 08/27/2002 | US6442091 Sense amplifier |
| 08/27/2002 | US6442090 Differential sensing amplifier for content addressable memory |
| 08/27/2002 | US6442089 Multi-level, low voltage swing sensing scheme for high speed memory design |
| 08/27/2002 | US6442088 Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory |
| 08/27/2002 | US6442087 Semiconductor memory device with reduced interference between bit lines |
| 08/27/2002 | US6442081 Semiconductor storage device data sensing method and apparatus |
| 08/27/2002 | US6442078 Semiconductor memory device having structure implementing high data transfer rate |
| 08/27/2002 | US6442077 Controlling reading from and writing to a semiconductor memory device |
| 08/27/2002 | US6442054 Sense amplifier for content addressable memory |
| 08/27/2002 | US6439457 Method and system for personalized message storage and retrieval |
| 08/22/2002 | WO2002049034A3 Amplifier for reading storage cells with exclusive-or type function |
| 08/22/2002 | WO2002046873A9 System and method for managing information objects |
| 08/22/2002 | US20020116657 Command input circuit having command acquisition units which acquire a series of commands in synchronization with respective edges of clock signal |
| 08/22/2002 | US20020114210 Semiconductor memory device and information processing unit |
| 08/22/2002 | US20020114209 Dynamic random access memory device and semiconductor integrated circuit device |
| 08/22/2002 | US20020114207 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells |
| 08/22/2002 | US20020114206 Data memory with a plurality of memory banks |
| 08/22/2002 | US20020114201 Semiconductor memory circuit |
| 08/22/2002 | US20020114195 Integrated circuit devices having delay circuits for controlling setup/delay times of data signals that are provided to memory devices and methods of operating same |
| 08/22/2002 | US20020114181 Multiple ports memory-cell structure |
| 08/22/2002 | US20020114178 Semiconductor memory device and memory system |
| 08/22/2002 | US20020113904 Two-dimensional buffer pages using bit-field addressing |
| 08/22/2002 | US20020113783 Display driver and display unit and electronic apparatus utilizing the same |
| 08/22/2002 | US20020113253 Semiconductor memory device |
| 08/22/2002 | US20020113251 Redundant circuit and method for replacing defective memory cells in a memory device |
| 08/21/2002 | EP1233420A1 Method and circuit for dynamic reading of a memory cell at low supply voltage and with low output dynamics |
| 08/21/2002 | EP1233417A2 Command input circuit |
| 08/21/2002 | CN1365116A Storage unit read-out based on non-contineous property |
| 08/21/2002 | CN1089489C Set circuit for operation mode of semiconductor device |
| 08/21/2002 | CN1089476C Video RAM and method for outputting serial data |
| 08/21/2002 | CN1089473C Synchronous semicondcutor memory device having an auto-precharge function |
| 08/20/2002 | US6438719 Memory supervision |
| 08/20/2002 | US6438669 Timesharing internal bus, particularly for non-volatile memories |
| 08/20/2002 | US6438667 Semiconductor memory and memory system |
| 08/20/2002 | US6438645 Apparatus and structure for rapid enablement |
| 08/20/2002 | US6438068 Active terminate command in synchronous flash memory |
| 08/20/2002 | US6438067 Clock generating circuit ensuring a wide lock-allowing frequency range and allowing reduction in layout area as well as a semiconductor device provided with the same |
| 08/20/2002 | US6438066 Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system |
| 08/20/2002 | US6438063 Integrated circuit memory devices having selectable column addressing and methods of operating same |
| 08/20/2002 | US6438062 Multiple memory bank command for synchronous DRAMs |
| 08/20/2002 | US6438058 Integrated circuit containing a number of subcircuits |
| 08/20/2002 | US6438054 Semiconductor integrated circuit |
| 08/20/2002 | US6438051 Stabilized direct sensing memory architecture |
| 08/20/2002 | US6438049 Variable equilibrate voltage circuit for paired digit lines |
| 08/20/2002 | US6438042 Arrangement of bitline boosting capacitor in semiconductor memory device |
| 08/20/2002 | US6438038 Read circuit of nonvolatile semiconductor memory |
| 08/20/2002 | US6438035 Nonvolatile semiconductor storage device |
| 08/20/2002 | US6438023 Double-edged clocked storage device and method |
| 08/20/2002 | US6438017 Read/write eight-slot CAM with interleaving |
| 08/20/2002 | US6438015 Semiconductor memory device and memory system for improving bus efficiency |
| 08/20/2002 | US6438013 Semiconductor integrated circuit and method for adjusting characteristics of the same |
| 08/20/2002 | US6437959 Electrical and/or electronic system integrated with an isolating device and method that isolates a functional module |
| 08/20/2002 | US6437619 Clock generation circuit, control method of clock generation circuit, clock reproducing circuit, semiconductor memory device, and dynamic random access memory |
| 08/20/2002 | US6437613 Clock generating circuit for compensation of delay difference using closed loop analog synchronous mirror delay structure |
| 08/20/2002 | US6437605 Dynamic sense amplifier for low-power applications |
| 08/20/2002 | US6437601 Using a timing strobe for synchronization and validation in a digital logic device |
| 08/20/2002 | US6437410 Integrated memory |
| 08/20/2002 | US6436725 Method of manufacturing semiconductor device using redundancy technique |
| 08/15/2002 | WO2002063629A1 High speed signal path and method |
| 08/15/2002 | WO2002008901A3 Partitioned random access memory |
| 08/15/2002 | US20020112101 Flash memory card with enhanced operating mode detection and user-friendly interfacing system |
| 08/15/2002 | US20020110939 Semiconductor device and method of inspecting the same |
| 08/15/2002 | US20020110351 Checkerboard buffer |
| 08/15/2002 | US20020110043 Integrated memory having a plurality of memory cell arrays and method for operating the integrated memory |
| 08/15/2002 | US20020110038 Fast random access DRAM management method |
| 08/15/2002 | US20020110037 Dram interface circuit providing continuous access across row boundaries |
| 08/15/2002 | US20020110036 Static memory cell having independent data holding voltage |
| 08/15/2002 | US20020110034 Input-output circuit and current control circuit of semiconductor memory device |
| 08/15/2002 | US20020110031 Zero margin enable controlling apparatus and method of sense amplifier adapted to semiconductor memory device |
| 08/15/2002 | US20020110030 Swapped Pixel pages |
| 08/15/2002 | US20020110017 Voltage generator for semiconductor device |
| 08/15/2002 | US20020110016 Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof |
| 08/15/2002 | US20020110015 Reduced area sense amplifier isolation layout in a dynamic ram architecture |
| 08/15/2002 | US20020110014 Recording system, data recording apparatus, memory apparatus, and data recording method |
| 08/15/2002 | US20020109792 Two-dimensional buffer pages using memory bank alternation |
| 08/15/2002 | US20020109791 Two-dimensional buffer pages |
| 08/15/2002 | US20020109699 Pixel pages optimized for GLV |
| 08/15/2002 | US20020109698 Checkerboard buffer using memory blocks |
| 08/15/2002 | US20020109696 Checkerboard buffer using two-dimensional buffer pages and using memory bank alternation |
| 08/15/2002 | US20020109695 Checkerboard buffer using two-dimensional buffer pages and using state addressing |
| 08/15/2002 | US20020109694 Checkerboard buffer using two-dimensional buffer pages and using bit-field addressing |
| 08/15/2002 | US20020109693 Checkerboard buffer using two-dimensional buffer pages |
| 08/15/2002 | US20020109692 Dynamic buffer pages |
| 08/15/2002 | US20020109691 Two-dimensional buffer pages using state addressing |
| 08/15/2002 | US20020109690 Checkerboard buffer using memory bank alternation |
| 08/15/2002 | US20020109689 Checkerboard buffer using sequential memory locations |
| 08/15/2002 | US20020109531 Sense amplifier drive circuit |
| 08/15/2002 | US20020109154 Integrated circuit memory devices providing per-bit redundancy and methods of operating same |
| 08/15/2002 | US20020109138 Programmable memory address and decode circuits with ultra thin vertical body transistors |
| 08/14/2002 | EP1231606A1 Semiconductor device |
| 08/14/2002 | EP1147518B1 Integrated electric and/or electronic system with means for insulating a functional module, corresponding device and method for insulation and use |
| 08/14/2002 | EP0953229A4 Method, system, and device for accumulating data and maintaining the accumulated data |
| 08/14/2002 | DE10205693A1 Halbleiterspeicherbauelement und zugehöriges Signalleitungsanordnungsverfahren Semiconductor memory device and associated signal line arrangement method |