Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
12/2000
12/19/2000USRE36993 Dynamic random access memory device with the combined open/folded bit-line pair arrangement
12/19/2000US6163860 Layout for a semiconductor memory device having redundant elements
12/19/2000US6163832 Semiconductor memory device including plural blocks with a pipeline operation for carrying out operations in predetermined order
12/19/2000US6163502 Clocking to support interface of memory controller to external SRAM
12/19/2000US6163501 Synchronous semiconductor memory device
12/19/2000US6163500 Memory with combined synchronous burst and bus efficient functionality
12/19/2000US6163499 Programmable impedance output buffer drivers, semiconductor devices and static random access memories provided with a programmable impedance output port
12/19/2000US6163498 Methods and systems for column line selection in a memory device
12/19/2000US6163497 Semiconductor memory device
12/19/2000US6163496 Semiconductor memory device having a common column decoder shared by plurality of banks
12/19/2000US6163495 Architecture, method(s) and circuitry for low power memories
12/19/2000US6163493 Semiconductor integrated circuit device with large internal bus width, including memory and logic circuit
12/19/2000US6163491 Synchronous semiconductor memory device which can be inspected even with low speed tester
12/19/2000US6163486 Output circuit of semiconductor memory device
12/19/2000US6163485 Semiconductor integrated circuit data processing system
12/19/2000US6163482 One transistor EEPROM cell using ferro-electric spacer
12/19/2000US6163479 Method for performing analog over-program and under-program detection for a multistate memory cell
12/19/2000US6163477 MRAM device using magnetic field bias to improve reproducibility of memory cell switching
12/19/2000US6163476 Static-random-access-memory cell
12/19/2000US6163475 Bit line cross-over layout arrangement
12/19/2000US6163189 Latch circuit capable of reducing slew current
12/19/2000US6163177 Semiconductor integrated circuit device having output buffer
12/19/2000US6162673 Method of manufacturing SRAM cell
12/14/2000WO2000075929A1 Ferroelectric memory with two ferroelectric capacitors in memory cell and method of operating same
12/14/2000DE19946201C1 Voltage buffering arrangement in dynamic CMOS memory, i.e. DRAM
12/13/2000EP1059669A1 Integrated semiconductor read only memory device
12/13/2000CN1276905A Ferroelectric data processing device
12/12/2000US6161208 Storage subsystem including an error correcting cache and means for performing memory to memory transfers
12/12/2000US6161117 Waveform generation device and method
12/12/2000US6160754 Synchronous memory device of a wave pipeline structure
12/12/2000US6160753 Semiconductor integrated circuit device having main word lines and sub-word lines
12/12/2000US6160752 Semiconductor memory device
12/12/2000US6160751 Semiconductor memory device allowing efficient column selection
12/12/2000US6160749 Pump control circuit
12/12/2000US6160748 Apparatus and method for maintaining bit line charge state during a read operation
12/12/2000US6160747 Configuration for crosstalk attenuation in word lines of DRAM circuits
12/12/2000US6160746 Semiconductor memory with auto-tracking bit line precharge scheme
12/12/2000US6160744 Semiconductor memory device and defect remedying method thereof
12/12/2000US6160743 Self-timed data amplifier and method for an integrated circuit memory device
12/12/2000US6160742 Semiconductor memory device and data read method of device
12/12/2000US6160572 Tuner for cable modem
12/12/2000CA2188101C Semiconductor memory device having small chip size and redundancy access time
12/07/2000WO2000074219A1 Charge pump
12/07/2000WO2000074067A1 Improved multilevel dram
12/07/2000WO2000074066A1 Self-restoring single event upset (seu) hardened multiport memory cell
12/07/2000WO2000074065A1 Method and apparatus for hardening a static random access memory cell from single event upsets
12/07/2000WO2000074064A1 Single event upset (seu) hardened static random access memory cell
12/07/2000WO2000074063A1 Plateline sensing
12/07/2000WO2000074062A1 Electronic memory with disturb prevention function
12/07/2000WO2000043893A3 Method and apparatus for refreshing a semiconductor memory using idle memory cycles
12/07/2000DE19956461A1 Nichtflüchtige Halbleiterspeichereinrichtung, die Mehrfachbit-Daten speichert A non-volatile semiconductor memory device, the multi-bit data stores
12/07/2000DE19924567A1 Integrated memory with two-transistor, two-capacitor storage cells
12/07/2000DE19922765A1 Integrated memory device with reference potential e.g. for FRAM
12/06/2000EP1058271A1 CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching
12/06/2000EP1058270A1 Biasing stage for biasing the drain terminal of a nonvolatile memory cell during the read phase
12/06/2000EP1058269A1 Synchronous multilevel non-volatile memory and related reading method
12/06/2000EP1058268A2 Ferroelectric memory and semiconductor memory
12/06/2000EP1058267A2 Semiconductor memory
12/06/2000EP1057188A1 Magnetic random access memory with a reference memory array
12/06/2000EP1057187A1 Method of fabricating a magnetic random access memory
12/06/2000EP1057185A1 Current sense amplifier
12/05/2000US6158036 Merged memory and logic (MML) integrated circuits including built-in test circuits and methods
12/05/2000US6157992 Synchronous semiconductor memory having read data mask controlled output circuit
12/05/2000US6157990 Independent chip select for SRAM and DRAM in a multi-port RAM
12/05/2000US6157979 Programmable controlling device with non-volatile ferroelectric state-machines for restarting processor when power is restored with execution states retained in said non-volatile state-machines on power down
12/05/2000US6157690 Digital PLL circuit
12/05/2000US6157688 Signal transmission system for transmitting signals between LSI chips, receiver circuit for use in the signal transmission system, and semiconductor memory device applying the signal transmission system
12/05/2000US6157623 Apparatus and method for selectively outputting data using a MAC layer interface or a PCI bus interface
12/05/2000US6157588 Semiconductor memory device having hierarchical word line structure
12/05/2000US6157586 Memory device having potential control for increasing the operating margin at the start of a sensing cycle
12/05/2000US6157585 Redundancy circuit and method of ferroelectric memory device
12/05/2000US6157581 Semiconductor memory having a restore voltage control circuit
12/05/2000US6157580 Semiconductor memory device capable of easily controlling a reference ratio regardless of change of a process parameter
12/05/2000US6157578 Method and apparatus for accessing a memory device
12/05/2000US6157574 Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data
12/05/2000US6157573 Nonvolatile memory system, semiconductor memory, and writing method
12/05/2000US6157570 Program/erase endurance of EEPROM memory cells
12/05/2000US6157566 Reduced leakage DRAM storage unit
12/05/2000US6157565 Reduced leakage DRAM storage unit
12/05/2000US6157563 Ferroelectric memory system and method of driving the same
12/05/2000US6157557 CAM cell and memory employing such, used for both field configurable RAM and PLA
12/05/2000US6157219 Amplifier for a semiconductor device and a method of controlling the same
12/05/2000US6157216 Circuit driver on SOI for merged logic and memory circuits
12/05/2000US6157203 Input circuit with improved operating margin using a single input differential circuit
12/05/2000US6157061 Nonvolatile semiconductor memory device and method of manufacturing the same
12/05/2000US6157052 Semiconductor integrated circuit having three wiring layers
12/05/2000US6156601 Method of forming DRAM matrix of basic organizational units each with pair of capacitors with hexagon shaped planar portion
11/2000
11/30/2000WO2000072324A1 Local shielding for memory cells
11/30/2000WO2000042615A3 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
11/30/2000WO2000026941A3 Word line driver for semiconductor memories
11/29/2000EP1056095A2 Adjustable output driver circuit
11/29/2000EP1055165A2 Integrated dram with high speed interleaving
11/29/2000CN1274930A Non-volatile semiconductor memory capable of storing multidata
11/28/2000US6154864 Read only memory embedded in a dynamic random access memory
11/28/2000US6154821 Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
11/28/2000US6154417 Integrated circuit memory devices having synchronous wave pipelining capability and methods of operating same
11/28/2000US6154416 Column address decoder for two bit prefetch of semiconductor memory device and decoding method thereof
11/28/2000US6154415 Internal clock generation circuit of semiconductor device and method for generating internal clock
11/28/2000US6154414 Semiconductor memory device having a plurality of memory blocks
11/28/2000US6154411 Boosting circuit compensating for voltage fluctuation due to operation of load
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