Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
11/2000
11/14/2000US6147895 Ferroelectric memory with two ferroelectric capacitors in memory cell and method of operating same
11/14/2000US6147894 Method and apparatus for storing data using spin-polarized electrons
11/14/2000US6147544 Data transfer circuit transferring complementary data signals
11/14/2000US6147527 Internal clock generator
11/14/2000US6147525 Frequency multiplier circuit operable with an external reference clock signal having a frequency in a wide range
11/14/2000US6147514 Sense amplifier circuit
11/14/2000US6147512 Input buffer circuit
11/14/2000US6147387 Static random access memory
11/14/2000US6146943 Method for fabricating nonvolatile memory device
11/14/2000US6146904 Method of making a two transistor ferroelectric memory cell
11/14/2000CA2104193C Bi-channel electrode configuration for an addressing structure using an ionizable gaseous medium and method of operating it
11/09/2000WO2000067381A1 Frequency-multiplying delay locked loop
11/09/2000WO2000067380A1 Integrated circuit low leakage power circuitry for use with an advanced cmos process
11/09/2000WO2000067129A1 Memory control unit
11/09/2000WO2000041181A3 Seu hardening circuit
11/09/2000DE19934501C1 Synchronous integrated memory e.g. dynamic random-access memory
11/08/2000EP1050882A2 Methods for operating semiconductor memory devices and semiconductor memory devices
11/08/2000EP1050820A2 A semiconductor memory device with a large storage capacity memory and a fast speed memory
11/08/2000EP1050052A1 Non-volatile memory with improved sensing and method therefor
11/08/2000EP1050051A1 Memory device using a transistor and its fabrication method
11/08/2000CN1272696A Semiconductor storage device and method for fetch said device in test pattern
11/07/2000USH1915 Hybrid static RAM circuit
11/07/2000US6145063 Memory system and information processing system
11/07/2000US6145055 Cache memory having flags for inhibiting rewrite of replacement algorithm area corresponding to fault cell and information processing system having such a cache memory
11/07/2000US6144713 Delay locked loop circuit for controlling delay time with reduced lock-up time
11/07/2000US6144617 Synchronous semiconductor storage device
11/07/2000US6144615 Synchronous dynamic random access memory
11/07/2000US6144614 Semiconductor integrated circuit having a clock and latch circuits for performing synchronous switching operations
11/07/2000US6144613 Synchronous semiconductor memory
11/07/2000US6144612 Address decoder for a synchronous type memory capable of preventing multi-wordline selection
11/07/2000US6144611 Method for clearing memory contents and memory array capable of performing the same
11/07/2000US6144610 Distributed circuits to turn off word lines in a memory array
11/07/2000US6144608 Dual-port memory
11/07/2000US6144605 Refresh circuit for SDRAM
11/07/2000US6144603 Semiconductor memory device
11/07/2000US6144602 Semiconductor memory device
11/07/2000US6144601 Semiconductor memory having an improved reading circuit
11/07/2000US6144599 Semiconductor memory device
11/07/2000US6144598 Method and apparatus for efficiently testing rambus memory devices
11/07/2000US6144597 Memory device having a self-test function using sense amplifiers and a method for controlling a data writing operation in a test mode of the memory device
11/07/2000US6144596 Semiconductor memory test apparatus
11/07/2000US6144595 Semiconductor device performing test operation under proper conditions
11/07/2000US6144593 Circuit and method for a multiplexed redundancy scheme in a memory device
11/07/2000US6144590 Semiconductor memory having differential bit lines
11/07/2000US6144588 Monolithically integrated generator of a plurality of voltage values
11/07/2000US6144587 Semiconductor memory device
11/07/2000US6144585 Semiconductor storage device for storing three-or multi-valued data in one memory cell
11/07/2000US6144583 Semiconductor integrated circuit device
11/07/2000US6144582 Nonvolatile semiconductor memory device
11/07/2000US6144579 Ferroelectric memory device
11/07/2000US6144578 Ferroelectric memory device and a method for manufacturing thereof
11/07/2000US6144577 Semiconductor memory device having multibit data bus and redundant circuit configuration with reduced chip area
11/07/2000US6144325 Register file array having a two-bit to four-bit encoder
11/07/2000US6144219 System and method for isolation of varying-power backed memory controller inputs
11/07/2000US6144055 Semiconductor memory device
11/07/2000US6143636 High density flash memory
11/07/2000US6142830 Signaling improvement using extended transmission lines on high speed DIMMS
11/02/2000WO2000065600A1 Static memory with four transistors unbalanced at their leakage current and method for controlling same
11/02/2000WO2000065599A1 Static memory with four transistors unbalanced at their drain-source current in standby status and method for controlling same
11/02/2000EP1049104A1 Technique for testing bitline and related circuitry of a memory array
11/02/2000EP1049103A1 Techniue for testing wordline and related circuitry of a memory array
11/02/2000EP1049101A2 Semiconductor memory cell
11/02/2000EP1049017A1 Semiconductor memory device with redundancy
11/02/2000EP0809884B1 Sense amplifier with pull-up circuit for accelerated latching of logic level output data
11/02/2000DE19961135A1 Voltage detection circuit for use in semiconductor memory component, includes compensation current generation section for preventing potential of signalling line VPP from rising steeply
11/02/2000DE19919360A1 Integrated memory device
11/02/2000DE19917589C1 Halbleiterspeicher vom wahlfreien Zugriffstyp Semiconductor memory of the random access type
11/02/2000DE19917588A1 Halbleiterspeicheranordnung mit BIST A semiconductor memory device with BIST
11/02/2000DE10020554A1 Semiconductor memory component with column selection circuit for selecting one of memory banks from memory block and for selecting specific bit line from selected bank, for use in e.g. Rambus DRAM
11/01/2000CN1271944A Integrated memory arranged with reading amplifier on opposite sides of cell area
11/01/2000CN1271943A Improved readout amplifier
11/01/2000CN1271942A Integrated memory possessing bit line, word line and plate line and its working method
10/2000
10/31/2000USRE36932 Semiconductor memory device operating stably under low power supply voltage with low power consumption
10/31/2000US6141292 Clock generating circuits that utilize analog pump signals to provide fast synchronization and reduced delay skew
10/31/2000US6141291 Semiconductor memory device
10/31/2000US6141290 Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals
10/31/2000US6141289 Structure of random access memory formed of multibit cells
10/31/2000US6141288 Semiconductor memory device allowing change of refresh mode and address switching method therewith
10/31/2000US6141287 Memory architecture with multilevel hierarchy
10/31/2000US6141286 Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines
10/31/2000US6141285 Power down scheme for regulated sense amplifier power in dram
10/31/2000US6141284 Method and apparatus for an improved reset and power-on arrangement for DRAM generator controller
10/31/2000US6141282 Circuit for designating an operating mode of a semiconductor memory device
10/31/2000US6141280 Refresh period automatic detecting device for semiconductor memory device, method of automatically detecting refresh period, and refresh period output device
10/31/2000US6141279 Refresh control circuit
10/31/2000US6141278 Semiconductor memory device allowing fast successive selection of word lines in a test mode operation
10/31/2000US6141275 Method of and apparatus for precharging and equalizing local input/output signal lines within a memory circuit
10/31/2000US6141274 Semiconductor integrated circuit having a pre-charged operation and a data latch function
10/31/2000US6141271 Circuits for testing memory devices having direct access test mode and methods for testing the same
10/31/2000US6141270 Method for cell margin testing a dynamic cell plate sensing memory architecture
10/31/2000US6141269 Semiconductor integrated circuit device using BiCMOS technology
10/31/2000US6141268 Column redundancy in semiconductor memories
10/31/2000US6141267 Defect management engine for semiconductor memories and memory systems
10/31/2000US6141265 Clock synchronous memory
10/31/2000US6141264 Floating isolation gate for DRAM sensing
10/31/2000US6141262 Boosting circuit with boosted voltage limited
10/31/2000US6141261 DRAM that stores multiple bits per storage cell
10/31/2000US6141260 Single electron resistor memory device and method for use thereof
10/31/2000US6141259 Dynamic random access memory having reduced array voltage
10/31/2000US6141258 Programmable impedance output buffer drivers, semiconductor devices and static random access memories provided with a progammable impedance output port
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