Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
05/2001
05/22/2001US6236243 Negative voltage level detection circuit
05/22/2001US6236117 Semiconductor memory device including shunt interconnection
05/22/2001US6235573 Methods of forming ferroelectric random access memory devices having shared capacitor electrodes
05/22/2001US6235212 Method of manufacture of an electrostatic ink jet printer
05/22/2001US6235211 Method of manufacture of an image creation apparatus
05/22/2001US6234609 High Young's modulus thermoelastic ink jet printing mechanism
05/17/2001US20010001322 Method of manufacturing SRAM cell
05/17/2001US20010001262 Semiconductor device
05/17/2001US20010001261 Circuit for resetting a pair of data buses of a semiconductor memory device
05/17/2001DE10027003A1 Halbleiterschaltungsvorrichtung mit der Fähigkeit, Stromversorgungspotentiale extern an eine interne Schaltung anzulegen und dabei Rauschen einzuschränken Semiconductor integrated circuit device with the ability to create electricity supply potentials external to an internal circuit and thereby reduce noise
05/16/2001EP1100199A2 Semiconductor device
05/16/2001EP1100090A1 Synchronous LSI memory device
05/16/2001EP1100089A1 Semiconductor memory device, and method of controlling the same
05/16/2001EP1099224A2 Circuit for generating a reference voltage for reading out from a ferroelectric memory
05/16/2001EP1099223A1 Storage assembly comprised of a plurality of resistive ferroelectric storage cells
05/16/2001EP1099222A2 Ferroelectric read/write memory having series-connected storage cells (cfram)
05/16/2001EP1099221A2 Magnetoresistive memory with low current density
05/16/2001CN1295333A Semiconductor integrated circuit device capable of inhibiting noise and supplying power potential
05/16/2001CN1295332A MRAM device having digital detection amplifier
05/15/2001USRE37176 Semiconductor memory
05/15/2001US6233717 Multi-bit memory device having error check and correction circuit and method for checking and correcting data errors therein
05/15/2001US6233707 Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clock
05/15/2001US6233705 Test method for data storage characteristics of memory
05/15/2001US6233199 Full page increment/decrement burst for DDR SDRAM/SGRAM
05/15/2001US6233196 Multi-bank integrated circuit memory devices with diagonal pairs of sub-banks
05/15/2001US6233195 Multi-bank DRAM suitable for integration with processor on common semiconductor chip
05/15/2001US6233193 Dynamic random access memory system with a static random access memory interface and methods for using the same
05/15/2001US6233192 Semiconductor memory device
05/15/2001US6233190 Method of storing a temperature threshold in an integrated circuit, method of modifying operation of dynamic random access memory in response to temperature, programmable temperature sensing circuit and memory integrated circuit
05/15/2001US6233188 Precharge control signal generating circuit
05/15/2001US6233187 Semiconductor memory device
05/15/2001US6233183 Semiconductor memory device with high data access speed
05/15/2001US6233181 Semiconductor memory device with improved flexible redundancy scheme
05/15/2001US6233179 Circuit and method for reading and writing data in a memory device
05/15/2001US6233175 Self-limiting multi-level programming states
05/15/2001US6233174 Non volatile semiconductor, memory
05/15/2001US6233173 Apparatus and method for selecting data bits read from a multistate memory
05/15/2001US6233172 Magnetic element with dual magnetic states and fabrication method thereof
05/15/2001US6233171 Superconducting magnetoresistive memory element using controlled exchange interaction
05/15/2001US6233170 Sense amplifier circuit, memory device using the circuit and method for reading the memory device
05/15/2001US6233169 Signal storing circuit semiconductor device, gate array and IC-card
05/15/2001US6232824 Semiconductor device capable of suppressing transient variation in level of internal power supply potential
05/15/2001US6232822 Semiconductor device including a bipolar transistor biased to produce a negative base current by the impact ionization mechanism
05/15/2001US6232813 Phase locked loop integrated circuits having fuse-enabled and fuse-disabled delay devices therein
05/15/2001US6232812 Integrated circuit delay lines having programmable and phase matching delay characteristics
05/15/2001US6232800 Differential sense amplifier circuit and dynamic logic circuit using the same
05/15/2001US6232797 Integrated circuit devices having data buffer control circuitry therein that accounts for clock irregularities
05/15/2001US6232795 Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same
05/15/2001US6232777 Tunneling magnetoresistive element and magnetic sensor using the same
05/15/2001US6232643 Memory using insulator traps
05/15/2001US6232173 Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure
05/15/2001US6231772 Method of manufacture of an iris motion ink jet printer
05/15/2001US6231163 Stacked electrostatic ink jet printing mechanism
05/10/2001WO2001033633A1 Semiconductor memory and method of driving semiconductor memory
05/10/2001US20010000991 Semiconductor memory device
05/10/2001US20010000990 Semiconductor memory device
05/10/2001US20010000989 Boosted-voltage drive circuit operable with high reliability and semiconductor memory device employing the same
05/10/2001US20010000952 Clock control method and circuit
05/10/2001US20010000949 Integrated circuit memory devices having programmable output driver circuits therein
05/10/2001DE19952311A1 Integrated memory with 2-transistor, 2 capacitor memory cells of different design than conventional ones, enabling pre-charging potential selection for 2 bit lines connected to memory cell
05/10/2001DE19952258A1 Integrated memory with folded bit line structure
05/10/2001DE19949713A1 Magnetoresistive layer system for giant magnetoresistive or tunnel magnetoresistive sensor or magnetic storage element, has structured surface in reference layer to prevent influence of external fields
05/10/2001DE10052326A1 Semiconductor remanent memory device with maintained margin between threshold voltages, for use in read-only memory type units
05/10/2001DE10042621A1 Semiconductor memory e.g. DRAM has control circuit which activates/deactivates memory row, in response to read/write and refreshing modes
05/10/2001DE10037973A1 Data output circuit has buffer stage containing pull-up and pull-down transistors, high and low level data output control stages and substrate potential switching stage
05/10/2001DE10022697A1 Dynamic random access memory outputs test-mode-entry signal in response to address key, if write-enable and column-address-trigger signals are output before activation of row address trigger signal
05/10/2001DE10019805A1 Dynamische Halbleiterspeichervorrichtung mit reduziertem Stromverbrauch im Lesebetrieb Dynamic semiconductor memory device with reduced power consumption in the reading operation
05/09/2001EP1098324A2 Ferroelectric non-volatile latch circuits
05/09/2001EP1097458A1 Storage assembly consisting of resistive ferroelectric storage cells
05/09/2001EP1097457A2 Storage cell system in which an electric resistance of a storage element represents an information unit and can be influenced by a magnetic field, and method for producing same
05/09/2001EP1097456A1 Universal memory element and method of programming same
05/09/2001EP1097455A1 Method and apparatus for controlling the data rate of a clocking circuit
05/09/2001EP0789917B1 Method and structure for controlling internal operations of a dram array
05/09/2001CN1294390A Field response reinforced magnetic component and its mfg. method
05/08/2001US6230280 Synchronous semiconductor memory device capable of generating stable internal voltage
05/08/2001US6230245 Method and apparatus for generating a variable sequence of memory device command signals
05/08/2001US6230235 Address lookup DRAM aging
05/08/2001US6229758 Semiconductor memory device that can read out data faster than writing it
05/08/2001US6229756 Semiconductor memory device capable of preventing mis-operation due to load of column address line
05/08/2001US6229755 Wordline driving apparatus in semiconductor memory devices
05/08/2001US6229753 Semiconductor memory device capable of accurate control of internally produced power supply potential
05/08/2001US6229752 Semiconductor integrated circuit device
05/08/2001US6229749 Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals
05/08/2001US6229748 Memory device using one common bus line between address buffer and row predecoder
05/08/2001US6229747 Self-refresh apparatus for a semiconductor memory device
05/08/2001US6229745 Semiconductor memory
05/08/2001US6229737 Method and apparatus for initializing semiconductor memory
05/08/2001US6229730 Ferroelectric memory device retaining ROM data
05/08/2001US6229729 Magneto resistor sensor with diode short for a non-volatile random access ferromagnetic memory
05/08/2001US6229728 Ferroelectric memory and method of testing the same
05/08/2001US6229383 Internal power-source potential supply circuit, step-up potential generating system, output potential supply circuit, and semiconductor memory
05/08/2001US6229379 Generation of negative voltage using reference voltage
05/08/2001US6229368 Internal clock generating circuits having delay compensation and methods for using the same
05/08/2001US6229365 Semiconductor integrated circuit device operating stably at a plurality of power supply voltage levels
05/08/2001US6229363 Semiconductor device
05/08/2001US6229340 Semiconductor integrated circuit
05/08/2001US6229332 Superconductive logic gate and random access memory
05/08/2001US6229186 Semiconductor memory device using inverter configuration
05/08/2001US6229161 Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches
05/08/2001US6228668 Method of manufacture of a thermally actuated ink jet printer having a series of thermal actuator units