Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
06/2001
06/05/2001US6243020 Method and apparatus for programmably driving an LED display
06/05/2001US6242954 Timing clock generation circuit using hierarchical DLL circuit
06/05/2001US6242940 Data input buffer circuit
06/05/2001US6242939 Superconducting circuit having superconductive circuit device of voltage-type logic and superconductive circuit device of fluxoid-type logic device selectively used therein
06/05/2001US6242812 CSP pin configuration compatible with TSOP pin configuration
06/05/2001US6242772 Multi-sided capacitor in an integrated circuit
06/05/2001US6241921 Electrophoretic separation of first and second particles within a circularly contained and encapsulated suspension, fusing the particles to form opposing optical elements
06/05/2001US6241904 Method of manufacture of a two plate reverse firing electromagnetic ink jet printer
06/05/2001US6241342 Lorentz diaphragm electromagnetic ink jet printing mechanism
06/05/2001CA2241126C Computer memory controller
05/2001
05/31/2001WO2001039196A1 Memory device
05/31/2001WO2001039195A1 Spin dependent tunneling memory
05/31/2001WO2001039194A1 Single-event upset hardened reconfigurable bi-stable cmos latch
05/31/2001US20010002461 Circuit and method for specifying performance parameters in integrated circuits
05/31/2001US20010002180 Dram with intermediate storage cache and separate read and write I/O
05/31/2001US20010002179 LSI device with memory and logics mounted thereon
05/31/2001US20010002178 Destructive read type memory circuit, restoring circuit for the same and sense amplifier
05/31/2001US20010002175 Semiconductor memory device having function of supplying stable power supply voltage
05/31/2001US20010002174 Plash EEprom system
05/31/2001US20010002172 Nonvolatile semiconductor memory device
05/31/2001US20010002112 Method and apparatus for the replacement of non-operational metal lines in DRAMS
05/31/2001US20010002062 High density SRAM cell with latched vertical transistors
05/31/2001DE19957124A1 Testing memory cells with hysteresis curve e.g. for FRAM
05/31/2001DE19956240A1 Read and refresh control method for DRAM memory used in a microcontroller system, involves periodic refreshing of DRAM during specified wait periods of CPU
05/31/2001DE19956069A1 Integrierter Speicher mit Speicherzellen und Referenzzellen Integrated memory having memory cells and reference cells
05/31/2001DE19955779A1 Data storage device especially semiconductor memory, such as RAM or ROM
05/31/2001DE19955601A1 Auto-refresh sequences actuating arrangement for dynamic random access memory (DRAM)
05/31/2001DE10054595A1 Non-volatile ferroelectric storage cell comprises gate electrodes on an active region of a substrate, ferroelectric layers with electrodes and metallizations
05/31/2001DE10054141A1 Delay control circuit for synchronous dynamic direct access memory has delay model for delaying external clock signal according to asymmetry, control signal generator, two delay devices
05/30/2001EP1104092A2 Operational amplifier with digital offset calibration
05/30/2001EP1103980A2 2-bit/cell type nonvolatile semiconductor memory
05/30/2001EP1103979A1 Dynamic random access memory (DRAM) and reading method thereof
05/30/2001EP1103051A1 Ferroelectric storage assembly
05/30/2001EP1103050A1 Resistive ferroelectric storage cell
05/30/2001EP1103049A2 Magnetic memory
05/30/2001CN1297566A Semiconductor storage device
05/29/2001US6240495 Memory control system and memory control method
05/29/2001US6240049 Synchronous semiconductor storage device
05/29/2001US6240048 Synchronous type semiconductor memory system with less power consumption
05/29/2001US6240046 Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle
05/29/2001US6240045 Synchronous semiconductor integrated circuit capable of improving immunity from malfunctions
05/29/2001US6240042 Output circuit for a double data rate dynamic random access memory, double data rate dynamic random access memory, method of clocking data out from a double data rate dynamic random access memory and method of providing a data strobe signal
05/29/2001US6240041 Signal generator with timing margin by using control signal to control different circuit
05/29/2001US6240039 Semiconductor memory device and driving signal generator therefor
05/29/2001US6240038 Low area impact technique for doubling the write data bandwidth of a memory array
05/29/2001US6240037 Dynamic random access memory device having booster against battery exhaustion
05/29/2001US6240036 Voltage supply circuit in a semiconductor memory device
05/29/2001US6240035 Semiconductor integrated circuit device and method of activating the same
05/29/2001US6240033 Antifuse circuitry for post-package DRAM repair
05/29/2001US6240032 Non-volatile semiconductor memory allowing user to enter various refresh commands
05/29/2001US6240026 Bit line sense circuit and method for dynamic random access memories
05/29/2001US6240024 Method and apparatus for generating an echo clock in a memory
05/29/2001US6240015 Method for reading 2-bit ETOX cells using gate induced drain leakage current
05/29/2001US6240014 Semiconductor memory device
05/29/2001US6240013 Data holding apparatus
05/29/2001US6240010 Semiconductor memory cell
05/29/2001US6240009 Asymmetric ram cell
05/29/2001US6240008 Read zero DRAM
05/29/2001US6240007 Nonvolatile ferroelectric memory device having global and local bitlines and split workline driver
05/29/2001US6240006 Semiconductor memory device having reduced interconnection resistance
05/29/2001US6239958 Electrostatic damage protection circuit and dynamic random access memory
05/29/2001US6239821 Direct firing thermal bend actuator ink jet printing mechanism
05/29/2001US6239647 Decoder circuit and decoding method of the same
05/29/2001US6239635 Self-timing control circuit
05/29/2001US6239633 Digital DLL circuit
05/29/2001US6239631 Integrated circuit device with input buffer capable of correspondence with highspeed clock
05/29/2001US6239457 Semiconductor memory device and manufacturing method thereof
05/29/2001US6238040 Thermally actuated slotted chamber wall ink jet printing mechanism
05/24/2001US20010001600 Method of controlling the conduction of the access transistors of a load less, four transistor memory cell
05/24/2001US20010001599 Memory structure utilizing four transistor load less memory cells and a bias generator
05/24/2001US20010001598 Dynamic random access memory (RAM), semiconductor storage device, and semiconductor integrated circuit (IC) device
05/24/2001US20010001597 Semiconductor storage device and method of driving thereof
05/24/2001US20010001545 Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor
05/23/2001EP1102168A2 Integrated memory with memory cells and reference cells
05/23/2001EP0928484B1 Charge sharing detection circuit for anti-fuses
05/23/2001EP0786780B1 Data output control circuit of semiconductor memory device having pipeline structure
05/23/2001EP0591811B1 Dynamic random access memory device having a parallel testing mode for producing arbitrary test pattern
05/23/2001DE10053962A1 Non-volatile ferroelectric memory has two sub-word lines connected to gates of respective transistors and connected to shunt lines
05/23/2001DE10043191A1 Non-volatile ferroelectric memory has column redundancy selection circuit that omits failed column address of main cell array block by replacing column with column of redundancy cell array block
05/23/2001DE10022698A1 Halbleiterspeichereinrichtung A semiconductor memory device
05/23/2001CN1296624A Semiconductor memory asynchronous pipeline
05/22/2001US6237122 Semiconductor memory device having scan flip-flops
05/22/2001US6236654 Method and apparatus for managing learning in an address table in memory
05/22/2001US6236643 Multiport data switch having variable maximum packet length
05/22/2001US6236619 Synchronous dynamic random access memory semiconductor device having write-interrupt-write function
05/22/2001US6236616 Semiconductor memory device having data input/output line shared by a plurality of banks
05/22/2001US6236615 Semiconductor memory device having memory cell blocks different in data storage capacity without influence on peripheral circuits
05/22/2001US6236614 Semiconductor memory with local phase generation from global phase signals and local isolation signals
05/22/2001US6236613 Semiconductor integrated circuit device having a hierarchical power source configuration
05/22/2001US6236611 Peak program current reduction apparatus and method
05/22/2001US6236607 Integrated memory having a reference potential and operating method for such a memory
05/22/2001US6236604 Row address circuit of semiconductor memory device and row addressing method in refresh mode
05/22/2001US6236601 Semiconductor memory device having faulty cells
05/22/2001US6236598 Clamping circuit for cell plate in DRAM
05/22/2001US6236590 Optimal write conductors layout for improved performance in MRAM
05/22/2001US6236588 Nonvolatile ferroelectric random access memory device and a method of reading data thereof
05/22/2001US6236587 Read-only memory and read-only memory devices
05/22/2001US6236586 Micro magnetic core memory
05/22/2001US6236581 High voltage boosted word line supply charge pump and regulator for DRAM
05/22/2001US6236258 Wordline driver circuit using ring-shaped devices