| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
|---|
| 04/19/2001 | WO2001027931A1 Multiple level flash memory |
| 04/19/2001 | WO2001027930A1 Nonvolatile memory for storing multibit data |
| 04/19/2001 | WO2001027929A1 Four-terminal eeprom cell for storing an analog voltage and memory system using the same to store multiple bits per eeprom cell |
| 04/19/2001 | WO2001027928A1 Memory that stores multiple bits per storage cell |
| 04/19/2001 | US20010000309 Semiconductor device |
| 04/19/2001 | US20010000308 Method of modifying the current conducted by the access transistors of a load less, four transistor memory cell |
| 04/19/2001 | US20010000307 Memory structure utilizing four transistor load less memory cells and a bias generator |
| 04/19/2001 | US20010000306 High density flash memory architecture with columnar substrate coding |
| 04/19/2001 | DE19946490A1 Magnetoresistiver Schreib/Lese-Speicher sowie Verfahren zum Beschreiben und Auslesen eines solchen Speichers A magnetoresistive read / write memory as well as methods for writing and reading out of such a memory |
| 04/19/2001 | DE10049362A1 Clock synchronous semiconductor memory has amplitude increase circuit that produces pair of complementary internal read data signals with amplitude level same as external power supply voltage |
| 04/18/2001 | EP1093228A1 Delay interpolator circuit and semiconductor integrated circuit having same |
| 04/18/2001 | EP1093127A1 Semiconductor memory |
| 04/18/2001 | EP1068620A4 High resolution multi-bit-per-cell memory |
| 04/18/2001 | EP0965132A4 Precision programming of nonvolatile memory cells |
| 04/17/2001 | US6219687 Method and apparatus for an N-nary Sum/HPG gate |
| 04/17/2001 | US6219686 Method and apparatus for an N-NARY sum/HPG adder/subtractor gate |
| 04/17/2001 | US6219300 Semiconductor device |
| 04/17/2001 | US6219298 High-speed address decoders and related address decoding methods |
| 04/17/2001 | US6219297 Dynamic random access memory that can be controlled by a controller for a less integrated dynamic random access memory |
| 04/17/2001 | US6219294 Multiplexed noisy-quiet power busing for improved area efficiencies and pause performance in DRAM memories |
| 04/17/2001 | US6219293 Method and apparatus for supplying regulated power to memory device components |
| 04/17/2001 | US6219292 Semiconductor memory device having reduced power requirements during refresh operation by performing refresh operation in a burst method |
| 04/17/2001 | US6219291 Reduction of data dependent power supply noise when sensing the state of a memory cell |
| 04/17/2001 | US6219288 Memory having user programmable AC timings |
| 04/17/2001 | US6219285 Semiconductor storage device with synchronized selection of normal and redundant columns |
| 04/17/2001 | US6219276 Multilevel cell programming |
| 04/17/2001 | US6219275 Magnetic thin film element, memory element using the same, and method for recording and reproducing using the memory element |
| 04/17/2001 | US6219273 Integrated semiconductor-magnetic random access memory system |
| 04/17/2001 | US6219272 Semiconductor random access memory |
| 04/17/2001 | US6219271 Semiconductor memory device |
| 04/17/2001 | US6219270 Integrated circuit having dynamic memory with boosted plateline |
| 04/17/2001 | US6219269 Semiconductor memory device capable of improving read operation speed |
| 04/17/2001 | US6219160 Optical logic element and methods for respectively its preparation and optical addressing, as well as the use thereof in an optical logic device |
| 04/17/2001 | US6218893 Power circuit and clock signal detection circuit |
| 04/17/2001 | US6218877 Semiconductor device with delay locked loop |
| 04/17/2001 | US6218713 Logical circuit, flip-flop circuit and storage circuit with multivalued logic |
| 04/17/2001 | US6218695 Area efficient column select circuitry for 2-bit non-volatile memory cells |
| 04/17/2001 | US6217165 Ink and media cartridge with axial ink chambers |
| 04/17/2001 | US6217153 Single bend actuator cupped paddle ink jet printing mechanism |
| 04/12/2001 | WO2001026156A1 Nonvolatile memory |
| 04/12/2001 | WO2001026139A2 Dram bit lines and support circuitry contacting scheme |
| 04/12/2001 | WO2001026113A1 Integrated circuit with a non-volatile mos ram cell |
| 04/12/2001 | US20010000213 Bias generator for a four transistor load less memory cell |
| 04/12/2001 | DE10049029A1 Circuit for determining latency of buffer circuit generates latency interval and latency indication from clock signal and from test signal derived from clock signal with delay |
| 04/12/2001 | DE10039612A1 Semiconductor device has address decoder detects accesses to overshoot i.e. non-used memory addresses using only part of the outputs of pre-decoders |
| 04/11/2001 | EP1091491A1 Input buffer for integrated circuit |
| 04/11/2001 | EP1091418A2 NROM cell with self-aligned programming and erasure areas |
| 04/11/2001 | EP1090342A1 Power failure mode for a memory controller |
| 04/11/2001 | EP1023731A4 Sense amplifier for flash memories |
| 04/11/2001 | EP0850480B1 Fast word line decoder for memory devices |
| 04/10/2001 | US6216246 Methods to make DRAM fully compatible with SRAM using error correction code (ECC) mechanism |
| 04/10/2001 | US6216147 Method and apparatus for an N-nary magnitude comparator |
| 04/10/2001 | US6216146 Method and apparatus for an N-nary adder gate |
| 04/10/2001 | US6215837 Pipe counter signal generator processing double data in semiconductor device |
| 04/10/2001 | US6215728 Data storage device capable of storing plural bits of data |
| 04/10/2001 | US6215726 Semiconductor device with internal clock generating circuit capable of generating internal clock signal with suppressed edge-to-edge jitter |
| 04/10/2001 | US6215724 Circuit and method for eliminating idle cycles in a memory device |
| 04/10/2001 | US6215723 Semiconductor memory device having sequentially disabling activated word lines |
| 04/10/2001 | US6215722 Command latency circuit for programmable SLDRAM and latency control method therefor |
| 04/10/2001 | US6215721 Multi-bank memory device and method for arranging input/output lines |
| 04/10/2001 | US6215719 Memory device having line address counter for making next line active while current line is processed |
| 04/10/2001 | US6215718 Architecture for large capacity high-speed random access memory |
| 04/10/2001 | US6215716 Static memory cell having independent data holding voltage |
| 04/10/2001 | US6215714 Semiconductor memory device capable of reducing power consumption in self-refresh operation |
| 04/10/2001 | US6215711 Row address strobe signal generating device |
| 04/10/2001 | US6215710 Apparatus and method for controlling data strobe signal in DDR SDRAM |
| 04/10/2001 | US6215708 Charge pump for improving memory cell low VCC performance without increasing gate oxide thickness |
| 04/10/2001 | US6215707 Charge conserving write method and system for an MRAM |
| 04/10/2001 | US6215704 Semiconductor memory device allowing reduction in a number of external pins |
| 04/10/2001 | US6215702 Method of maintaining constant erasing speeds for non-volatile memory cells |
| 04/10/2001 | US6215697 Multi-level memory cell device and method for self-converged programming |
| 04/10/2001 | US6215696 Ferromagnetic tunnel junction device and method of forming the same |
| 04/10/2001 | US6215695 Magnetoresistance element and magnetic memory device employing the same |
| 04/10/2001 | US6215694 Self-restoring single event upset (SEU) hardened multiport memory cell |
| 04/10/2001 | US6215693 Methods of operating ferroelectric memory devices having reconfigurable bit lines |
| 04/10/2001 | US6215692 Non-volatile ferroelectric memory |
| 04/10/2001 | US6215691 Cell structure of ferroelectric memory device |
| 04/10/2001 | US6215690 Semiconductor memory devices having shared data line contacts |
| 04/10/2001 | US6215689 Architecture, circuitry and method for configuring volatile and/or non-volatile memory for programmable logic applications |
| 04/10/2001 | US6215352 Reference voltage generating circuit with MOS transistors having a floating gate |
| 04/10/2001 | US6215349 Capacitive coupled driver circuit |
| 04/10/2001 | US6215336 Reference type input first stage circuit in a semiconductor integrated circuit |
| 04/10/2001 | US6215159 Semiconductor integrated circuit device |
| 04/10/2001 | US6215148 NROM cell with improved programming, erasing and cycling |
| 04/10/2001 | US6214244 Method of manufacture of a reverse spring lever ink jet printer |
| 04/10/2001 | US6213589 Planar thermoelastic bend actuator ink jet printing mechanism |
| 04/10/2001 | US6213588 Electrostatic ink jet printing mechanism |
| 04/05/2001 | WO2001024289A1 Magnetoresistance effect memory device and method for producing the same |
| 04/05/2001 | WO2001024267A1 Two transistor flash memory cell |
| 04/05/2001 | WO2001024266A1 Twisted bitlines architectures |
| 04/05/2001 | WO2001024190A1 Polyvalent, magnetoresistive write/read memory and method for writing and reading a memory of this type |
| 04/05/2001 | WO2001024189A1 Zero power sram precharge |
| 04/05/2001 | WO2001024188A1 Arrangement to reduce coupling noise between bitlines |
| 04/05/2001 | WO2001024187A1 Dynamic random access memory |
| 04/05/2001 | WO2001024185A1 Method and circuit for evaluating the information content of a memory cell |
| 04/05/2001 | WO2001024184A1 Configurable synchronizer for double data rate synchronous dynamic random access memory |
| 04/05/2001 | WO2001024102A1 Capacitive sensing array devices |
| 04/05/2001 | US20010000133 Semiconductor integrated circuit device and method of activating the same |
| 04/05/2001 | DE19947041A1 Integrated dynamic semiconducting memory with redundant units of memory cells enables high quality of memory wrt. holding time of cell contents, low test and repair costs |
| 04/05/2001 | DE10046413A1 Integrated semiconductor circuit e.g. static random access memory, outputs pulse signal in response to functional signal of input and clock signals without holding functional signal |