| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 07/03/2001 | US6256261 Memory device with packet command |
| 07/03/2001 | US6256260 Synchronous semiconductor memory device having input buffers and latch circuits |
| 07/03/2001 | US6256258 Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory |
| 07/03/2001 | US6256257 Memory device including a burn-in controller for enabling multiple wordiness during wafer burn-in |
| 07/03/2001 | US6256256 Dual port random access memories and systems using the same |
| 07/03/2001 | US6256254 Semiconductor memory device decoder |
| 07/03/2001 | US6256253 Memory device with support for unaligned access |
| 07/03/2001 | US6256252 Memory-embedded semiconductor integrated circuit device having low power consumption |
| 07/03/2001 | US6256251 Circuit with variable voltage boosting ratios in a memory device |
| 07/03/2001 | US6256249 Method for hidden DRAM refresh |
| 07/03/2001 | US6256248 Method and apparatus for increasing the time available for internal refresh for 1-T SRAM compatible devices |
| 07/03/2001 | US6256247 Differential sense amplifiers for resistive cross point memory cell arrays |
| 07/03/2001 | US6256246 Semiconductor memory device |
| 07/03/2001 | US6256245 Precharging apparatus and method in a semiconductor memory device |
| 07/03/2001 | US6256244 Self refresh apparatus in semiconductor memory device |
| 07/03/2001 | US6256240 Semiconductor memory circuit |
| 07/03/2001 | US6256238 Semiconductor memory device |
| 07/03/2001 | US6256236 Semiconductor device capable of implementing simultaneous signal input and output from and to the same external terminal |
| 07/03/2001 | US6256231 EEPROM array using 2-bit non-volatile memory cells and method of implementing same |
| 07/03/2001 | US6256230 Nonvolatile memory device and refreshing method |
| 07/03/2001 | US6256224 Write circuit for large MRAM arrays |
| 07/03/2001 | US6256223 Current-induced magnetic switching device and memory including the same |
| 07/03/2001 | US6256222 Magnetoresistance effect device, and magnetoresistaance effect type head, memory device, and amplifying device using the same |
| 07/03/2001 | US6256221 Arrays of two-transistor, one-capacitor dynamic random access memory cells with interdigitated bitlines |
| 07/03/2001 | US6256220 Ferroelectric memory with shunted isolated nodes |
| 07/03/2001 | US6256219 Integrated memory having memory cells disposed at crossover points of word lines and bit lines |
| 07/03/2001 | US6256218 Integrated circuit memory devices having adjacent input/output buffers and shift blocks |
| 07/03/2001 | US6255862 Latch type sense amplifier circuit |
| 07/03/2001 | US6254793 Method of manufacture of high Young's modulus thermoelastic inkjet printer |
| 07/03/2001 | US6254220 Shutter based ink jet printing mechanism |
| 06/28/2001 | WO2001046988A2 Method and apparatus for routing 1 of n signals |
| 06/28/2001 | US20010005373 Virtual channel DRAM |
| 06/28/2001 | US20010005334 Semiconductor memory device |
| 06/28/2001 | US20010005331 Dual-to -single-rail converter for the read out of static storage arrays |
| 06/28/2001 | US20010005330 Nand-type flash memory device and method of operating the same |
| 06/28/2001 | US20010005327 Negative resistance device |
| 06/28/2001 | US20010005326 Method for writing and reading a ferroelectric memory |
| 06/28/2001 | US20010005325 Semiconductor memory device |
| 06/28/2001 | US20010005160 Reference voltage generation circuit using source followers |
| 06/28/2001 | US20010005150 Latch type sense amplifier and method for operating thereof |
| 06/28/2001 | US20010005148 Semiconductor intergrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout |
| 06/28/2001 | US20010005147 Semiconductor circuit including output buffer circuit and drive circuit for driving output buffer circuit |
| 06/28/2001 | US20010005144 Configuration for testing a multiplicity of semiconductor chips |
| 06/28/2001 | US20010005027 Semiconductor memory circuit |
| 06/28/2001 | US20010005014 Semiconductor storage device having redundancy circuit for replacement of defect cells under tests |
| 06/28/2001 | US20010005013 Semiconductor integrated circuit and integrated circuit system |
| 06/28/2001 | US20010005012 Fast cycle ram having improved data write operation |
| 06/28/2001 | US20010005011 Magnetic tunnel junction device, magnetic memory adopting the same, magnetic memory cell and access method of the same |
| 06/28/2001 | DE10053507A1 Semiconductor memory e.g. SRAM, has sense amp circuit with positive feedback circuit having differential pairs of P-channel type field effect transistors and gates of transistors in each pair are connected mutually |
| 06/27/2001 | EP1111782A2 Differential sense amplifier circuit and dynamic logic circuit using the same |
| 06/27/2001 | EP1111620A2 A negative resistance device |
| 06/27/2001 | EP1111619A2 Peak program current reduction apparatus and method |
| 06/27/2001 | EP1110378A1 Random access method for blocks of video images |
| 06/27/2001 | CN1301043A Multi-stage quick EEPROM unit and manufacture thereof |
| 06/27/2001 | CN1301024A Differential reading-out amplifying circuit and dynamic logic circuit for using it |
| 06/26/2001 | US6253298 Synchronous SRAM having pipelined enable |
| 06/26/2001 | US6252820 Semiconductor memory device capable of monitoring and adjusting the timing and pulse width of internal control signals |
| 06/26/2001 | US6252816 Circuit and method for refreshing data stored in a memory cell |
| 06/26/2001 | US6252812 Semiconductor memory device utilizing multiple edges of a signal |
| 06/26/2001 | US6252808 Semiconductor memory device having improved row redundancy scheme and method for curing defective cell |
| 06/26/2001 | US6252807 Memory device with reduced power consumption when byte-unit accessed |
| 06/26/2001 | US6252806 Multi-generator, partial array Vt tracking system to improve array retention time |
| 06/26/2001 | US6252805 Semiconductor memory device including programmable output pin determining unit and method of reading the same during test mode |
| 06/26/2001 | US6252804 Semiconductor integrated circuit, and method of controlling same |
| 06/26/2001 | US6252801 Nonvolatile semiconductor memory device |
| 06/26/2001 | US6252796 Device comprising a first and a second ferromagnetic layer separated by a non-magnetic spacer layer |
| 06/26/2001 | US6252795 Programmable resistive circuit using magnetoresistive memory technology |
| 06/26/2001 | US6252794 DRAM and data access method for DRAM |
| 06/26/2001 | US6252793 Reference cell configuration for a 1T/1C ferroelectric memory |
| 06/26/2001 | US6252788 Semiconductor integrated circuit device |
| 06/26/2001 | US6252471 Programmable oscillator using magnetoresistive memory technology |
| 06/26/2001 | US6252448 Coincident complementary clock generator for logic circuits |
| 06/26/2001 | US6252431 Shared PMOS sense amplifier |
| 06/26/2001 | US6252425 Method and apparatus for an N-NARY logic circuit |
| 06/26/2001 | US6252263 Layout structure for dynamic random access memory |
| 06/26/2001 | US6251713 Method of making an SRAM storage cell with N channel thin film transistor load devices |
| 06/26/2001 | US6251298 Method of manufacture of a planar swing grill electromagnetic ink jet printer |
| 06/21/2001 | WO2001045161A1 Nonvolatile memory and method of driving nonvolatile memory |
| 06/21/2001 | WO2001045110A1 Data storage device and corresponding method |
| 06/21/2001 | WO2001045108A1 Programmable resistance memory arrays with reference cells |
| 06/21/2001 | US20010004335 Synchronous double data rate dram |
| 06/21/2001 | US20010004332 NROM cell with improved programming, erasing and cycling |
| 06/21/2001 | US20010004331 Semiconductor storage device |
| 06/21/2001 | US20010004329 Semiconductor memory device |
| 06/21/2001 | US20010004325 Nonvolatile memory cell and method for programming and/or verifying the same |
| 06/21/2001 | DE19960247A1 Datenspeicher und Verfahren Data storage and method |
| 06/20/2001 | EP1109170A2 Magnetic memory device |
| 06/20/2001 | EP1109169A2 MRAM having semiconductor device integrated therein |
| 06/20/2001 | EP1109168A2 Magnetic dual element with dual magnetic states and fabricating method thereof |
| 06/20/2001 | EP1108257A1 An mram cell requiring low switching field |
| 06/20/2001 | EP0710390B1 Magnetic structure with stratified layers |
| 06/20/2001 | CN1300431A Method and apparatus for a serial access memory |
| 06/20/2001 | CN1300077A MRAM with integrated semiconducter device |
| 06/19/2001 | USRE37232 Delay circuit device |
| 06/19/2001 | US6249841 Integrated circuit memory device and method incorporating flash and ferroelectric random access memory arrays |
| 06/19/2001 | US6249521 Method and apparatus for creating a port vector |
| 06/19/2001 | US6249483 Semiconductor memory device having a circuit for latching data from a data line of a data output path and a related data latching method |
| 06/19/2001 | US6249477 Semiconductor memory device |
| 06/19/2001 | US6249476 Semiconductor memory device suitable for mounting mixed with logic circuit, having short cycle time in reading operation |
| 06/19/2001 | US6249474 Semiconductor memory device for multi-bit or multi-bank architectures |