| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 07/26/2001 | WO2001001450A3 Dram cell fabrication process and method for operating same |
| 07/26/2001 | US20010010057 Semiconductor integrated circuit, computer system, data processor and data processing method |
| 07/26/2001 | US20010009531 Memory device having a variable data output length |
| 07/26/2001 | US20010009530 Semiconductor memory device |
| 07/26/2001 | US20010009529 Column select latch for SDRAM |
| 07/26/2001 | US20010009528 Method for storing a temperature threshold in an integrated circuit, method for storing a temperature threshold in a dynaic random access memory, method of modifying dynamic random access memory operation in response to temperature, programmable temperature sensing circuit and memory integrated circuit |
| 07/26/2001 | US20010009526 Bi-directional differential low power sense amp and memory system |
| 07/26/2001 | US20010009525 Word-line deficiency detection method for semiconductor memory device |
| 07/26/2001 | US20010009524 Semiconductor device having a test circuit |
| 07/26/2001 | US20010009521 Semiconductor memory device with improved flexible redundancy scheme |
| 07/26/2001 | US20010009520 Non-volatile memory device |
| 07/26/2001 | US20010009519 Dynamic ram and semiconductor device |
| 07/26/2001 | US20010009518 High voltage boosted word line supply charge pump and regulator for dram |
| 07/26/2001 | US20010009289 Flash memory device and fabrication method thereof |
| 07/26/2001 | US20010009276 Memory device having a variable data output length and a programmable register |
| 07/26/2001 | US20010009275 Clock synchronization circuit and semiconductor device having the same |
| 07/26/2001 | DE10064206A1 Delay lock loop for use in semiconductor memory device has OR gate which performs OR operation of output signals of bidirectional delay blocks, and outputs signal as final internal clock signal |
| 07/25/2001 | EP1119004A1 Semiconductor memory with refresh controller and method for refreshing the content of a semiconductor memory |
| 07/25/2001 | EP1118081A1 Integrated memory with differential read amplifier |
| 07/25/2001 | EP1118080A1 Decoder element for producing an output signal with three different potentials |
| 07/25/2001 | EP0904588B1 A device and method for multi-level charge/storage and reading out |
| 07/25/2001 | EP0886864B1 Programming flash memory using distributed learning methods |
| 07/25/2001 | EP0766866B1 A continuous page random access memory and systems and methods using the same |
| 07/25/2001 | EP0740837B1 Method and circuitry for storing discrete amounts of charge in a single memory element |
| 07/25/2001 | CN1305234A Magnetic tunnel device, magnetic storage and element using said device and its access method |
| 07/24/2001 | US6266738 Memory control providing controllable rate of refresh operations |
| 07/24/2001 | US6266737 Method and apparatus for providing a memory with write enable information |
| 07/24/2001 | US6266294 Integrated circuit device |
| 07/24/2001 | US6266292 DRAM core refresh with reduced spike current |
| 07/24/2001 | US6266289 Method of toroid write and read, memory cell and memory device for realizing the same |
| 07/24/2001 | US6266288 Methods for reducing the effects of power supply distribution related noise |
| 07/24/2001 | US6266287 Variable equilibrate voltage circuit for paired digit lines |
| 07/24/2001 | US6266286 Wafer burn-in test circuit and method for testing a semiconductor memory device |
| 07/24/2001 | US6266285 Method of operating a memory device having write latency |
| 07/24/2001 | US6266283 Semiconductor memory device |
| 07/24/2001 | US6266282 Write method of synchronous flash memory device sharing a system bus with a synchronous random access memory device |
| 07/24/2001 | US6266281 Method of erasing non-volatile memory cells |
| 07/24/2001 | US6266279 Nonvolatile semiconductor memory device, method for reading data from the nonvolatile semiconductor memory device, and method for writing data into the nonvolatile semiconductor memory device |
| 07/24/2001 | US6266278 Dual floating gate EEPROM cell array with steering gates shared adjacent cells |
| 07/24/2001 | US6266272 Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells |
| 07/24/2001 | US6266270 Non-volatile semiconductor memory and programming method of the same |
| 07/24/2001 | US6266267 Single conductor inductive sensor for a non-volatile random access ferromagnetic memory |
| 07/24/2001 | US6266266 Integrated circuit design exhibiting reduced capacitance |
| 07/24/2001 | US6266265 Memory module using a vacant pin terminal for balancing parasitic capacitive loads |
| 07/24/2001 | US6266264 Word line straps using two different layers of metal |
| 07/24/2001 | US6265932 Substrate control voltage circuit of a semiconductor memory |
| 07/24/2001 | US6265918 Clock signal processing circuit and semiconductor device in which a clock signal is processed in improved method |
| 07/24/2001 | US6265906 Sense amplifier circuit |
| 07/24/2001 | US6265748 Storage cell arrangement in which vertical MOS transistors have at least three different threshold voltages depending on stored data, and method of producing said arrangement |
| 07/24/2001 | US6265738 Thin film ferroelectric capacitors having improved memory retention through the use of essentially smooth bottom electrode structures |
| 07/24/2001 | US6264850 Dual nozzle single horizontal fulcrum actuator inkjet |
| 07/24/2001 | US6264849 Method of manufacture of a bend actuator direct ink supply ink jet printer |
| 07/24/2001 | US6264307 Buckle grill oscillating pressure ink jet printing mechanism |
| 07/24/2001 | US6264306 Linear spring electromagnetic grill ink jet printing mechanism |
| 07/24/2001 | CA2257740C Method and apparatus of column redundancy for non-volatile analog and multilevel memory integrated circuits |
| 07/24/2001 | CA2211699C Nonvolatile magnetoresistive memory with fully closed-flux operation |
| 07/24/2001 | CA2017607C Integrated memory comprising a sense amplifier |
| 07/19/2001 | WO2001052266A1 Substrates carrying polymers of linked sandwich coordination compounds and methods of use thereof |
| 07/19/2001 | WO2001052265A2 Decoder circuit |
| 07/19/2001 | WO2001052264A1 Dram that stores multiple bits per storage cell |
| 07/19/2001 | WO2001051188A2 High-density non-volatile memory devices incorporating thiol-derivatized porphyrin trimers |
| 07/19/2001 | US20010009022 Adaptive memory control |
| 07/19/2001 | US20010008498 Fast accessible dynamic type semiconductor memory device |
| 07/19/2001 | US20010008497 Semiconductor device |
| 07/19/2001 | US20010008496 Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory |
| 07/19/2001 | US20010008495 Synchronous Semiconductor memory device |
| 07/19/2001 | US20010008494 Semiconductor memory |
| 07/19/2001 | US20010008492 Semiconductor memory and method for controlling the same |
| 07/19/2001 | US20010008491 Semiconductor device with dram and logic part integrated |
| 07/19/2001 | US20010008489 Electrically alterable non-volatile memory with n-bits per cell |
| 07/19/2001 | US20010008488 Semiconductor integrated circuit |
| 07/19/2001 | US20010008282 Semiconductor memory device |
| 07/19/2001 | US20010008281 Method for writing data to semiconductor memory and semiconductor memory |
| 07/19/2001 | US20010008280 Semiconductor integrated circuit |
| 07/19/2001 | DE10101630A1 Halbleiterspeicherbauelement mit Eingabe-/Ausgabeleitungsstruktur Semiconductor memory device with input / output line structure |
| 07/19/2001 | DE10063732A1 Halbleiterspeicherbauelement mit hierarchischer Wortleitungsstruktur Semiconductor memory device with a hierarchical word line structure |
| 07/19/2001 | DE10063631A1 Virtual channel synchronized with a dynamic RAM for driving memory cells uses a semiconductor memory device with a base cell structure for a word driver, a main decoder and a reader booster for reading out information from the cells. |
| 07/19/2001 | DE10061604A1 Halbleiterspeicher, der mit einem Reihenadressendecodierer versehen ist, der eine reduzierte Signalausbreitungsverzögerungszeit hat A semiconductor memory, which is provided with a row address decoder, which has a reduced signal propagation delay time |
| 07/19/2001 | DE10060665A1 Nichtflüchtiger ferroelektrischer Speicher und Verfahren zu dessen Herstellung A non-volatile ferroelectric memory and method for its production |
| 07/19/2001 | DE10001648A1 IC with several sub-circuits with relatively short time required to set reference value for each controllable voltage source provided by sub-circuits |
| 07/19/2001 | CA2396568A1 Substrates carrying polymers of linked sandwich coordination compounds and methods of use thereof |
| 07/18/2001 | EP1117136A1 Ferromagnetic double quantum well tunnel magneto-resistance device |
| 07/18/2001 | EP1116248A1 Method of manufacturing a magnetic tunnel junction device |
| 07/18/2001 | EP1116241A2 A method and a device for testing a memory array in which fault response is compressed |
| 07/18/2001 | EP1116237A1 Block write circuit and method for wide data path memory devices |
| 07/18/2001 | EP1116043A1 Method of manufacturing a magnetic tunnel junction device |
| 07/18/2001 | CN1304179A Nonvolatile semiconductor storage device |
| 07/18/2001 | CN1304140A Simiconductor storage device |
| 07/17/2001 | US6263413 Memory integrated circuit and main memory and graphics memory systems applying the above |
| 07/17/2001 | US6263400 Memory cells configurable as CAM or RAM in programmable logic devices |
| 07/17/2001 | US6263398 Integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache |
| 07/17/2001 | US6262940 Semiconductor memory device and method for improving the transmission data rate of a data input and output bus and memory module |
| 07/17/2001 | US6262939 Semiconductor integrated circuit device |
| 07/17/2001 | US6262938 Synchronous DRAM having posted CAS latency and method for controlling CAS latency |
| 07/17/2001 | US6262937 Synchronous random access memory having a read/write address bus and process for writing to and reading from the same |
| 07/17/2001 | US6262936 Random access memory having independent read port and write port and process for writing to and reading from the same |
| 07/17/2001 | US6262935 Shift redundancy scheme for wordlines in memory circuits |
| 07/17/2001 | US6262934 Memory circuit including word line reset circuit and method of resetting word line |
| 07/17/2001 | US6262931 Semiconductor memory device having voltage down convertor reducing current consumption |
| 07/17/2001 | US6262922 Semiconductor memory device |