| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
|---|
| 08/16/2001 | US20010014050 Semiconductor memory device and bit line connecting method thereof |
| 08/16/2001 | US20010014049 Apparatus and method for thermal regulation in memory subsystems |
| 08/16/2001 | US20010014048 Delay locked loop with delay control unit for noise elimination |
| 08/16/2001 | US20010014047 Semiconductor memory device including an SOI substrate |
| 08/16/2001 | US20010014046 Semiconductor memory device for fast access |
| 08/16/2001 | US20010014045 Memory circuit for preventing rise cell array power source |
| 08/16/2001 | US20010014044 Semiconductor memory device exhibiting improved high speed and stable write operations |
| 08/16/2001 | US20010014042 Semiconductor device, semiconductor memory device and semiconductor integrated circuit device |
| 08/16/2001 | US20010014040 Semiconductor memory device having program circuit |
| 08/16/2001 | US20010014030 Layout design method on semiconductor chip for avoiding detour wiring |
| 08/16/2001 | US20010014002 Semiconductor device having mechanism capable of high-speed operation |
| 08/16/2001 | US20010013776 Magnetic field sensor with perpendicular axis sensitivity, comprising a giant magnetoresistance material of a spin tunnel junction |
| 08/16/2001 | US20010013769 Voltage conversion circuit and control circuit therefor |
| 08/16/2001 | US20010013659 Semiconductor memory device having a multi-layer interconnection structure suitable for merging with logic |
| 08/16/2001 | EP1124231A1 Memory circuit with shorter access time |
| 08/16/2001 | EP1124230A1 Multiple message multilevel analog signal recording and playback system having memory array configurable for analog and digital storage and serial communication |
| 08/16/2001 | EP0835527B1 A stack/trench diode for use with a multi-state material in a non-volatile memory cell |
| 08/16/2001 | DE19949713C2 Magnetoresistives Schichtsystem The magnetoresistive layer system |
| 08/16/2001 | DE10061769A1 Halbleiterspeicherbaustein A semiconductor memory device |
| 08/15/2001 | CN1308763A Ferroelectric read/write memory having series-connected storage cell (CFRAM) |
| 08/15/2001 | CN1308338A Integrated semiconductor memory with memory units of ferroelectric storage effect |
| 08/15/2001 | CN1308317A Magnetoresistive element and magnetic memory device |
| 08/14/2001 | US6275963 Test circuit and a redundancy circuit for an internal memory circuit |
| 08/14/2001 | US6275895 Memory refreshing system |
| 08/14/2001 | US6275841 1-of-4 multiplier |
| 08/14/2001 | US6275838 Method and apparatus for an enhanced floating point unit with graphics and integer capabilities |
| 08/14/2001 | US6275440 Semiconductor integrated circuit device and method of activating the same |
| 08/14/2001 | US6275439 Power supply control apparatus for changing power line connection type in response to operation mode in semiconductor memory device |
| 08/14/2001 | US6275438 Circuit for applying power to static random access memory cell |
| 08/14/2001 | US6275437 Refresh-type memory with zero write recovery time and no maximum cycle time |
| 08/14/2001 | US6275434 Semiconductor memory |
| 08/14/2001 | US6275433 Four transistor SRAM cell with improved read access |
| 08/14/2001 | US6275432 Method of reading and writing data using local data read and local data write circuits |
| 08/14/2001 | US6275431 Semiconductor memory device having bit line precharge circuits activated by separate control signals and control method for the same |
| 08/14/2001 | US6275430 Semiconductor memory device having global bit line precharge circuits |
| 08/14/2001 | US6275429 Memory device and equalizing circuit for memory device |
| 08/14/2001 | US6275425 Ferroelectric voltage boost circuits |
| 08/14/2001 | US6275423 Semiconductor memory device |
| 08/14/2001 | US6275420 Semiconductor device having memory cell part and transfer circuit |
| 08/14/2001 | US6275419 Multi-state memory |
| 08/14/2001 | US6275417 Multiple level flash memory |
| 08/14/2001 | US6275411 Spin dependent tunneling memory |
| 08/14/2001 | US6275409 Methods of operating a dynamic random access memory |
| 08/14/2001 | US6275408 Ferroelectric memory and method |
| 08/14/2001 | US6275091 Clock signal control circuit and method and synchronous delay circuit |
| 08/14/2001 | US6275086 Clock signal generator for an integrated circuit |
| 08/14/2001 | US6275080 Enhanced single event upset immune latch circuit |
| 08/14/2001 | US6275069 Self-resetting logic circuits and method of operation thereof |
| 08/14/2001 | US6274928 Single deposition layer metal dynamic random access memory |
| 08/14/2001 | US6274912 Semiconductor memory cell and method of manufacturing the same |
| 08/14/2001 | US6274895 Semiconductor integrated circuit device |
| 08/10/2001 | CA2335195A1 Multiple message multilevel analog signal recording and playback system having memory array configurable for analog and digital storage and serial communication |
| 08/09/2001 | WO2001057876A2 Flash memory cell and method to achieve multiple bits per cell |
| 08/09/2001 | WO2001057875A1 Semiconductor device |
| 08/09/2001 | WO2001057873A1 Integrated semiconductor memory and method for resetting memory cells of an integrated semiconductor memory |
| 08/09/2001 | WO2001057506A1 High efficiency magnetic sensor for magnetic particles |
| 08/09/2001 | US20010013081 Memory consolidated image processing LSI, image processing system with same, and image accessing method using same |
| 08/09/2001 | US20010012290 Data input circuit and semiconductor device utilizing data input circuit |
| 08/09/2001 | US20010012234 Method and apparatus for setting write latency |
| 08/09/2001 | US20010012233 Synchronous semiconductor memory device |
| 08/09/2001 | US20010012232 Semiconductor integrated circuit |
| 08/09/2001 | US20010012231 Memory circuit/logic circuit integrated device capable of reducing term of works |
| 08/09/2001 | US20010012230 Semiconductor memory device capable of reducing power consumption in self-refresh operation |
| 08/09/2001 | US20010012228 Differential sense amplifiers for resistive cross point memory cell arrays |
| 08/09/2001 | US20010012227 Semiconductor memory device |
| 08/09/2001 | US20010012223 Semiconductor memory device and manufacturing method thereof which make it possible to improve reliability of cell-capacitor and also to simplify the manufacturing processes |
| 08/09/2001 | US20010012220 Method and apparatus for supplying regulated power to memory device components |
| 08/09/2001 | US20010012215 Multi-level dram trench store utilizing two capacitors and two plates |
| 08/09/2001 | US20010012214 Semiconductor memory device |
| 08/09/2001 | US20010012213 Ferroelectric memory array |
| 08/09/2001 | US20010011921 Internal power-source potential supply circuit, step-up potential generating system, output potential supply circuit, and semiconductor memory |
| 08/09/2001 | US20010011918 Semiconductor integrated circuit device |
| 08/09/2001 | US20010011916 Clock signal generator for an integrated circuit |
| 08/09/2001 | US20010011913 Apparatus and method for generating a clock within a semiconductor device and devices and systems including same |
| 08/09/2001 | US20010011886 Internal supply voltage generating circuit and method of generating internal supply voltage |
| 08/09/2001 | US20010011753 Semiconductor integrated circuit device and method of manufacturing thereof |
| 08/09/2001 | US20010011739 Ferroelectric random access memory device |
| 08/09/2001 | US20010011735 Semiconductor memory device for decreasing a coupling capacitance |
| 08/09/2001 | DE10065477A1 Automatic pre-charge device of semiconductor storage arrangement, includes automatic pre-charge signal generator for reception of external control signals and then for generating an internal pre-charge command signal |
| 08/09/2001 | DE10004648A1 Integrated semiconductor memory e.g. dynamic semiconductor memory, has connection line which outputs control signal to precharging and memory circuits and read amplifier |
| 08/09/2001 | DE10004110A1 Read/write control method of synchronous memory, involves autoprecharging signal paths separately during reading and writing processes |
| 08/09/2001 | DE10004109A1 Memory module of electronic data processor, has switch connecting main and local data lines, arranged such that delay time of bit during synchronous memory access is made shorter |
| 08/09/2001 | DE10004108C1 Circuit for generating output clock signal with optimised signal generation time for memory arrangement eliminates certain problems related to transition times - has duty cycle equaliser with 2 coupled symmetrical branches contg. multiplexer integrated with programmable signal supply points producing output signal |
| 08/08/2001 | EP1122740A1 Integrated semiconductor memory and method for clearing memory cells of an integrated semiconductor memory |
| 08/08/2001 | EP1122738A1 Circuit for generating an output clock signal with optimised signal generation time |
| 08/08/2001 | EP1122734A1 Burst interleaved memory with burst mode access in synchronous read phases wherein the two sub-arrays are independently readable with random access during asynchronous read phases |
| 08/08/2001 | EP1122713A2 Memory consolidated image processing LSI, image processing system with same, and image accessing method using same |
| 08/08/2001 | EP1086465A4 Method and apparatus for a serial access memory |
| 08/08/2001 | EP1004119A4 A dynamic random access memory system with simultaneous access and refresh operations and methods for using the same |
| 08/07/2001 | USRE37316 Synchronous LSI memory device |
| 08/07/2001 | US6272608 Method and apparatus for synchronous data transfers in a memory device with lookahead logic for detecting latency intervals |
| 08/07/2001 | US6272588 Method and apparatus for verifying and characterizing data retention time in a DRAM using built-in test circuitry |
| 08/07/2001 | US6272586 Memory system having programmable control parameters |
| 08/07/2001 | US6272577 Data processing system with master and slave devices and asymmetric signal swing bus |
| 08/07/2001 | US6272567 System for interposing a multi-port internally cached DRAM in a control path for temporarily storing multicast start of packet data until such can be passed |
| 08/07/2001 | US6272321 Method for tuning an oscillating receiver circuit of a transponder built into a RFID system |
| 08/07/2001 | US6272070 Method and apparatus for setting write latency |
| 08/07/2001 | US6272069 LSI device with memory and logics mounted thereon |
| 08/07/2001 | US6272068 Integrated circuit memory devices that utilize data masking techniques to facilitate test mode analysis |
| 08/07/2001 | US6272067 SRAM synchronized with an optimized clock signal based on a delay and an external clock |