| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 08/29/2001 | EP1127378A1 Ferroelectric thin films of reduced tetragonality |
| 08/29/2001 | EP1127354A1 Ferroelectric memory with increased switching voltage |
| 08/29/2001 | EP0901682B1 Read amplifier for semiconductor memory cells with means to compensate threshold voltage differences in read amplifier transistors |
| 08/29/2001 | EP0830682B1 Auto-activate on synchronous dynamic random access memory |
| 08/29/2001 | EP0755559B1 Memory array utilizing multi-state memory cells |
| 08/29/2001 | CN1310845A Resistive ferroelectric storage cell |
| 08/29/2001 | CN1310844A Ferroelectric storage assembly |
| 08/29/2001 | CN1310481A Magnet resistor and magnetic memory using the same magnetoresistance apparatus |
| 08/29/2001 | CN1310448A Ferroelectric memory device with ferroelectric capacitor |
| 08/28/2001 | US6282606 Dynamic random access memories with hidden refresh and utilizing one-transistor, one-capacitor cells, systems and methods |
| 08/28/2001 | US6282603 Memory with pipelined accessed and priority precharge |
| 08/28/2001 | US6282150 Semiconductor memory device |
| 08/28/2001 | US6282147 Semiconductor memory device having word lines driven by row selecting signal and column selecting signal lines arranged parallel to each other |
| 08/28/2001 | US6282145 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
| 08/28/2001 | US6282143 Multi-port static random access memory design for column interleaved arrays |
| 08/28/2001 | US6282142 Semiconductor memory device |
| 08/28/2001 | US6282141 Semiconductor memory device and memory system |
| 08/28/2001 | US6282140 Multiplexor having a single event upset (SEU) immune data keeper circuit |
| 08/28/2001 | US6282137 SRAM method and apparatus |
| 08/28/2001 | US6282133 Semiconductor memory device having a delay circuit for generating a read timing |
| 08/28/2001 | US6282128 Integrated circuit memory devices having multiple data rate mode capability and methods of operating same |
| 08/28/2001 | US6282124 Method of erasing a flash EEPROM memory cell array optimized for low power consumption |
| 08/28/2001 | US6282120 Non-volatile memory with improved sensing and method therefor |
| 08/28/2001 | US6282119 Mixed program and sense architecture using dual-step voltage scheme in multi-level data storage in flash memories |
| 08/28/2001 | US6282117 Nonvolatile semiconductor memory device |
| 08/28/2001 | US6282116 Dynamic random access memory |
| 08/28/2001 | US6282115 Multi-level DRAM trench store utilizing two capacitors and two plates |
| 08/28/2001 | US6282113 Four F-squared gapless dual layer bitline DRAM array architecture |
| 08/28/2001 | US6281760 On-chip temperature sensor and oscillator for reduced self-refresh current for dynamic random access memory |
| 08/28/2001 | US6281739 Fuse circuit and redundant decoder |
| 08/28/2001 | US6281728 Delay locked loop circuit |
| 08/28/2001 | US6281725 Semiconductor integrated circuit having a clock recovery circuit |
| 08/28/2001 | US6281713 Current sense amplifiers having equalization circuits therin that inhibit signal oscillations during active modes |
| 08/28/2001 | US6281665 High speed internal voltage generator with reduced current draw |
| 08/28/2001 | US6281545 Multi-level, split-gate, flash memory cell |
| 08/28/2001 | US6281519 Quantum semiconductor memory device including quantum dots |
| 08/23/2001 | WO2001061705A1 Memory device with support for unaligned access |
| 08/23/2001 | WO2001061703A2 Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks |
| 08/23/2001 | WO2001061502A1 Unauthorised modification of values stored in flash memory |
| 08/23/2001 | US20010016893 Layout for a semiconductor memory device having redundant elements |
| 08/23/2001 | US20010016381 Memory cell, memory device and method of fabricating the same |
| 08/23/2001 | US20010016022 Delay time adjusting circuit comprising frequency dividers having different frequency division rates |
| 08/23/2001 | US20010015934 Rambus dram |
| 08/23/2001 | US20010015933 Dual port programmable logic device variable depth and width memory array |
| 08/23/2001 | US20010015930 Semiconductor memory device |
| 08/23/2001 | US20010015929 Integrated circuit memory devices having multiple input/output buses and precharge circuitry for precharging the input/output buses between write operations |
| 08/23/2001 | US20010015928 Memory device with faster reset operation |
| 08/23/2001 | US20010015927 Synchronous semiconductor memory device having improved operational frequency margin at data input/output |
| 08/23/2001 | US20010015926 Semiconductor memory device and method for setting stress voltage |
| 08/23/2001 | US20010015916 Storage cells utilizing reduced pass gate voltages for read and write operations |
| 08/23/2001 | US20010015914 Integrated semiconductor memory |
| 08/23/2001 | US20010015909 Nonvolatile semiconductor memory and read method |
| 08/23/2001 | US20010015908 Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory |
| 08/23/2001 | US20010015907 Negative resistance memory cell and method |
| 08/23/2001 | US20010015906 Ferroelectric read/write memory with series-connected memory cells (CFRAM) |
| 08/23/2001 | US20010015905 System having memory devices operable in a common interface |
| 08/23/2001 | US20010015666 Semiconductor integrated circuit device, semiconductor memory system and clock synchronous circuit |
| 08/23/2001 | US20010015665 Synchronous type flip-flop circuit of semiconductor device |
| 08/23/2001 | US20010015664 Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero |
| 08/22/2001 | EP1126531A2 Magnetoresistance effect device, and magnetoresistance effect type head, memory device, and amplifying device using the same |
| 08/22/2001 | EP1126525A2 Semiconductor memory device, method for driving the same and method for fabricating the same |
| 08/22/2001 | EP1126471A1 Method for reading or writing from or into a ferroelectric transistor of a memory cell and a memory matrix |
| 08/22/2001 | EP1126470A2 Integrated semiconductor memory with memory cells having ferroelectric memory effect |
| 08/22/2001 | EP1126469A2 Magnetic memory |
| 08/22/2001 | EP1126468A2 MRAM device including differential sense amplifiers |
| 08/22/2001 | EP1125300A1 Method and apparatus for increasing the time available for refresh for 1-t sram compatible devices |
| 08/22/2001 | EP1125203A1 Column redundancy circuit with reduced signal path delay |
| 08/22/2001 | EP0763240B1 Bit map addressing schemes for flash memory |
| 08/22/2001 | EP0714545B1 Improved data output buffer |
| 08/22/2001 | CN1309810A Storage assembly comprised of plurality of resistive ferroelectric storage cells |
| 08/22/2001 | CN1309430A Magnetic tunnel junction element and magnetic memory using it |
| 08/22/2001 | CN1309301A Magnetic element with double magnetic state and mfg. method thereof |
| 08/21/2001 | US6279133 Method and apparatus for significantly improving the reliability of multilevel memory architecture |
| 08/21/2001 | US6279116 Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation |
| 08/21/2001 | US6279073 Configurable synchronizer for double data rate synchronous dynamic random access memory |
| 08/21/2001 | US6279071 System and method for column access in random access memories |
| 08/21/2001 | US6278653 Reduced skew timing scheme for write circuitry used in memory circuits |
| 08/21/2001 | US6278652 Input initial stage circuit for semiconductor memory |
| 08/21/2001 | US6278650 Semiconductor memory device capable of keeping sensing efficiency of data line sense amplifier uniform |
| 08/21/2001 | US6278648 Method for writing to multiple banks of a memory device |
| 08/21/2001 | US6278647 Semiconductor memory device having multi-bank and global data bus |
| 08/21/2001 | US6278644 Serial access memory having data registers shared in units of a plurality of columns |
| 08/21/2001 | US6278641 Method and apparatus capable of programmably delaying clock of DRAM |
| 08/21/2001 | US6278640 Dynamic memory word line driver scheme |
| 08/21/2001 | US6278638 Pulse generator circuit and semiconductor memory provided with the same |
| 08/21/2001 | US6278637 SRAM generating an echo clock signal |
| 08/21/2001 | US6278633 High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations |
| 08/21/2001 | US6278632 Method and circuitry for performing analog over-program and under-program detection for a multistate memory cell |
| 08/21/2001 | US6278631 Magnetic random access memory array divided into a plurality of memory banks |
| 08/21/2001 | US6278630 Ferroelectric memory device with a high-speed read circuit |
| 08/21/2001 | US6278628 Semiconductor integrated circuit |
| 08/21/2001 | US6278309 Method of controlling a clock signal and circuit for controlling a clock signal |
| 08/21/2001 | US6278303 Semiconductor device that can have standby current reduced by ceasing supply of clock signal, and that can maintain status of internal circuit |
| 08/21/2001 | US6278300 I/O interface circuit, semiconductor chip and semiconductor system |
| 08/21/2001 | US6278287 Isolated well transistor structure for mitigation of single event upsets |
| 08/21/2001 | US6278148 Semiconductor device having a shielding conductor |
| 08/21/2001 | CA2210643C Nonvolatile content addressable memory |
| 08/16/2001 | WO2001059573A1 Information processor and semiconductor integrated circuit |
| 08/16/2001 | US20010014922 Interface circuit device for performing data sampling at optimum strobe timing |
| 08/16/2001 | US20010014053 Output circuit for a double data rate dynamic random access memory, double data rate dynamic random access memory, method of clocking data out from a double data rate dynamic random access memory and method of providing a data strobe signal |