Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
09/2001
09/06/2001US20010019511 Semiconductor integrated circuit
09/06/2001US20010019504 DRAM circuit and method of controlling the same
09/06/2001US20010019503 Clock synchronous semiconductor memory device having a reduced access time
09/06/2001US20010019502 Semiconductor integrated circuit device having hierarchical power source arrangement
09/06/2001US20010019500 Electrically alterable non-volatile memory with n-bits per cell
09/06/2001US20010019498 Ferroelectric memory capable of suppressing deterioration of dummy cells and drive method therefor
09/06/2001US20010019497 Semiconductor memory device, method for driving the same and method for fabricating the same
09/06/2001US20010019286 Booster circuit
09/06/2001US20010019284 Integrated circuit
09/06/2001US20010019139 Circuit configuration for an integrated semiconductor memory with column access
09/06/2001DE10009346A1 Schreib-/Leseverstärker mit Vertikaltransistoren für DRAM-Speicher Read / Write Amplifier with vertical transistors for DRAM memory
09/05/2001EP1130778A2 Semiconductor register element
09/05/2001EP1130603A2 Dynamic random access memory device with enhanced bus turnaround
09/05/2001EP1130602A1 Semiconductor memory device with reduced current consumption in data hold mode
09/05/2001EP1130600A1 Data balancing scheme in solid state storage devices
09/05/2001EP1129366A1 Magnetoresistive sensor or memory elements with decreased magnetic switch field
09/05/2001EP0732701B1 Bit-line precharge current limiter for CMOS dynamic memories
09/05/2001CN1311892A Storage assembly consisting of resistive ferroelectric storage cells
09/05/2001CN1311532A Write amplifier/read amplifier having vertical transistor used for DRAM memory
09/04/2001US6286077 Synchronous semiconductor memory device with a plurality of memory modules which has an additional function for masking a data strobe signal outputted from each memory module
09/04/2001US6285723 Timing signal generation circuit
09/04/2001US6285626 Semiconductor device
09/04/2001US6285624 Multilevel memory access method
09/04/2001US6285623 Semiconductor memory
09/04/2001US6285622 Semiconductor device
09/04/2001US6285621 Method of minimizing the access time in semiconductor memories
09/04/2001US6285618 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
09/04/2001US6285617 Semiconductor memory device preventing malfunction during refresh operation even when noise is superimposed on control signal
09/04/2001US6285616 Memory refreshing control apparatus comprising a unique refreshing counter
09/04/2001US6285615 Multiple output current mirror with improved accuracy
09/04/2001US6285613 Semiconductor memory device
09/04/2001US6285612 Reduced bit line equalization level sensing scheme
09/04/2001US6285611 Memory device having input and output sense amplifiers that occupy less circuit area
09/04/2001US6285610 Burn-in test circuit
09/04/2001US6285606 Semiconductor memory device
09/04/2001US6285603 Repair circuit of semiconductor memory device
09/04/2001US6285602 Semiconductor memory device provided with I/O clamp circuit
09/04/2001US6285600 Device and method for supplying current to a semiconductor memory to support a boosted voltage within the memory during testing
09/04/2001US6285598 Precision programming of nonvolatile memory cells
09/04/2001US6285597 Semiconductor integrated circuit and data processing system
09/04/2001US6285596 Multi-level type nonvolatile semiconductor memory device
09/04/2001US6285595 Semiconductor memory having electrically erasable and programmable nonvolatile semiconductor memory cells
09/04/2001US6285593 Word-line decoder for multi-bit-per-cell and analog/multi-level memories with improved resolution and signal-to-noise ratio
09/04/2001US6285589 Non-volatile semiconductor memory apparatus
09/04/2001US6285582 Two-dimensional resonant tunneling diode memory system
09/04/2001US6285581 MRAM having semiconductor device integrated therein
09/04/2001US6285580 Method and apparatus for hardening a static random access memory cell from single event upsets
09/04/2001US6285579 System and method for enabling/disabling SRAM banks for memory access
09/04/2001US6285578 Hidden refresh pseudo SRAM and hidden refresh method
09/04/2001US6285577 Non-volatile memory using ferroelectric capacitor
09/04/2001US6285576 Nonvolatile ferroelectric memory
09/04/2001US6285575 Shadow RAM cell and non-volatile memory device employing ferroelectric capacitor and control method therefor
09/04/2001US6285574 Symmetric segmented memory array architecture
09/04/2001US6285573 Semiconductor integrated circuit having shield wire
09/04/2001US6285258 Offset voltage trimming circuit
09/04/2001US6285241 Internal voltage boosting circuit
09/04/2001US6285225 Delay locked loop circuits and methods of operation thereof
09/04/2001US6285222 Power-on reset circuit, and semiconductor device
09/04/2001US6285216 High speed output enable path and method for an integrated circuit device
09/04/2001US6284147 Method of manufacture of a stacked electrostatic ink jet printer
09/04/2001US6283582 Iris motion ink jet printing mechanism
09/03/2001CA2299991A1 A memory cell for embedded memories
08/2001
08/30/2001WO2001063616A1 Variable pulse width memory programming
08/30/2001WO2001063615A1 User selectable cell programming
08/30/2001WO2001063614A1 Mixed mode multi-level memory
08/30/2001WO2001063613A1 Multilevel cell programming
08/30/2001WO2000052697A9 Magneto resistor sensor with differential collectors for a non-volatile random access ferromagnetic memory
08/30/2001US20010018726 Memory refreshing system
08/30/2001US20010018725 Controlling reading from and writing to a semiconductor memory device
08/30/2001US20010017814 Semiconductor integrated circuit device with test interface circuit for performing test on embedded memory from outside
08/30/2001US20010017813 Semiconductor memory device
08/30/2001US20010017812 Negative voltage generating circuit with high control responsiveness which can be formed using transistor with low breakdown voltage and semiconductor memory device including the same
08/30/2001US20010017811 Semiconductor memory device
08/30/2001US20010017810 Semiconductor memory device
08/30/2001US20010017807 Semiconductor memory device allowing static-charge tolerance test between bit lines
08/30/2001US20010017805 Automatic precharge apparatus of semiconductor memory device
08/30/2001US20010017804 Semiconductor device, semiconductor memory device and test-mode entry method
08/30/2001US20010017803 Semiconductor memory
08/30/2001US20010017802 Semiconductor device and semiconductor device testing method
08/30/2001US20010017798 Semiconductor integrated circuit device and data processor device
08/30/2001US20010017796 Semiconductor memory device for distributing load of input and output lines
08/30/2001US20010017794 Semiconductor memory device
08/30/2001US20010017792 Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other
08/30/2001US20010017791 Dynamic random access memory (DRAM) having ATD circuit
08/30/2001US20010017790 Synchronous semiconductor memeory device and method for reading data
08/30/2001US20010017787 Semiconductor memory device
08/30/2001US20010017670 Method for random access to picture blocks in video pictures
08/30/2001US20010017628 Image memory chip and method for storing data
08/30/2001US20010017558 Semiconductor integrated circuit having a clock recovery circuit
08/30/2001US20010017553 Semiconductor device and method for generating internal power supply voltage
08/30/2001US20010017552 Semiconductor device and semiconductor device testing method
08/30/2001US20010017386 Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor
08/30/2001US20010017380 Semiconductor integrated circuit
08/30/2001DE10106860A1 Magnetic Tunnel Junction element has third magnetic layer on opposite side of second magnetic layer from first forming closed magnetic circuit in common with second magnetic layer
08/30/2001DE10101036A1 Schnittstellenschaltungsvorrichtung zum Ausführen einer Datenabtastung zum optimalen Freigabezeitpunkt Interface circuitry means for performing data sampling at the optimal release time
08/30/2001DE10059485A1 Circuit for activating SRAM banks for memory access has holding device that can change transfer device to data value without second device changing to another value during transfer
08/30/2001DE10007176A1 Dekodiervorrichtung Decoding
08/30/2001DE10005619A1 Integrierter Halbleiterspeicher mit Speicherzellen mit ferroelektrischem Speichereffekt Integrated semiconductor memory having memory cells with ferroelectric memory effect
08/29/2001EP1128389A1 Write/Sense amplifier with vertical transistors for DRAM
08/29/2001EP1128269A2 Method for addressing electrical fuses