| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 09/19/2002 | WO2002073623A1 Nonvolatile semiconductor storage device |
| 09/19/2002 | WO2002073621A1 Memory based on a four-transistor storage cell |
| 09/19/2002 | WO2002073620A2 Reference for mram cell |
| 09/19/2002 | WO2002073619A2 System latency levelization for read data |
| 09/19/2002 | WO2002073618A2 Memory sense amplifier for a semiconductor memory device |
| 09/19/2002 | US20020133770 Circuit and method for test and repair |
| 09/19/2002 | US20020133767 Circuit and method for test and repair |
| 09/19/2002 | US20020133750 Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits |
| 09/19/2002 | US20020133742 DRAM memory page operation method and its structure |
| 09/19/2002 | US20020133731 Duty cycle distortion compensation for the data output of a memory device |
| 09/19/2002 | US20020133666 System latency levelization for read data |
| 09/19/2002 | US20020133664 Cache memory |
| 09/19/2002 | US20020133663 Memory devices with reduced power consumption refresh cycles |
| 09/19/2002 | US20020133312 Setting data retention thresholds in charge-based memory |
| 09/19/2002 | US20020132441 Suppression of cross diffusion and gate depletion |
| 09/19/2002 | US20020132436 EEPROM array and method for operation thereof |
| 09/19/2002 | US20020131320 SRAM emulator |
| 09/19/2002 | US20020131318 Semiconductor device including multi-chip |
| 09/19/2002 | US20020131316 Semiconductor memory device and method of pre-charging I/O lines |
| 09/19/2002 | US20020131315 Multi-bank memory |
| 09/19/2002 | US20020131314 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions |
| 09/19/2002 | US20020131313 High frequency range four bit prefetch output data path |
| 09/19/2002 | US20020131312 Pseudo differential sensing method and apparatus for DRAM cell |
| 09/19/2002 | US20020131311 Balanced sense amplifier control for open digit line architecture memory devices |
| 09/19/2002 | US20020131309 Memory, writing apparatus, reading apparatus, writing method, and reading method |
| 09/19/2002 | US20020131308 Semiconductor Memory |
| 09/19/2002 | US20020131299 Non-volatile semiconductor memory device |
| 09/19/2002 | US20020131296 Magnetic material memory and information reproducing method of the same |
| 09/19/2002 | US20020131295 MRAM architecture and system |
| 09/19/2002 | US20020131294 SRAM cell with horizontal merged devices |
| 09/19/2002 | US20020131292 Semiconductor memory and its driving method |
| 09/19/2002 | US20020131291 Interleaved wordline architecture |
| 09/19/2002 | US20020130714 Semiconductor integrated circuit device having an optimal circuit layout to ensure stabilization of internal source voltages without lowering circuit functions and/or operating performance |
| 09/19/2002 | US20020130702 Voltage boosting circuit for an integrated circuit device |
| 09/19/2002 | US20020130699 Pump circuits using flyback effect from integrated inductance |
| 09/19/2002 | US20020130687 Antifuse reroute of dies |
| 09/19/2002 | US20020130683 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them |
| 09/19/2002 | US20020130344 Semiconductor device |
| 09/19/2002 | US20020130339 Magnetoresistance effect device, method of manufacturing the same, magnetic memory apparatus, personal digital assistance, and magnetic reproducing head, and magnetic information reproducing apparatus |
| 09/19/2002 | DE10203333A1 Halbleiterspeichereinrichtung mit Selbstauffrischmodus A semiconductor memory device with self refresh |
| 09/19/2002 | DE10153560A1 Memory arrangement with additional free space for data reading process has approximately constant sum of electrical resistances in reference voltage line and selected bit line |
| 09/19/2002 | DE10110625A1 Valuating read-out signal of read-out amplifier for dynamic semiconductor memory |
| 09/18/2002 | EP1241708A2 Semiconductor memory device with floating body |
| 09/18/2002 | EP1241676A1 Pseudo differential sensing method and apparatus for dram cell |
| 09/18/2002 | EP1088309B1 Writing and reading method for ferroelectric memory |
| 09/18/2002 | EP1060027B1 Circuit and method for specifying performance parameters in integrated circuits |
| 09/18/2002 | EP1040484B1 Method and system for processing pipelined memory commands |
| 09/17/2002 | US6453433 Reduced signal test for dynamic random access memory |
| 09/17/2002 | US6453400 Semiconductor integrated circuit device |
| 09/17/2002 | US6453399 Semiconductor memory device and computer having a synchronization signal indicating that the memory data output is valid |
| 09/17/2002 | US6453398 Multiple access self-testing memory |
| 09/17/2002 | US6452976 Data transfer circuit with reduced current consumption |
| 09/17/2002 | US6452892 Magnetic tunnel device, method of manufacture thereof, and magnetic head |
| 09/17/2002 | US6452867 Full page increment/decrement burst for DDR SDRAM/SGRAM |
| 09/17/2002 | US6452863 Method of operating a memory device having a variable data input length |
| 09/17/2002 | US6452862 Semiconductor memory device having hierarchical word line structure |
| 09/17/2002 | US6452861 Semiconductor memory device allowing simultaneous inputting of N data signals |
| 09/17/2002 | US6452860 Semiconductor memory device having segment type word line structure |
| 09/17/2002 | US6452859 Dynamic semiconductor memory device superior in refresh characteristics |
| 09/17/2002 | US6452858 Semiconductor device |
| 09/17/2002 | US6452855 DRAM array interchangeable between single-cell and twin-cell array operation |
| 09/17/2002 | US6452854 Circuit and method for supplying internal power to semiconductor memory device |
| 09/17/2002 | US6452853 Nonvolatile semiconductor memory |
| 09/17/2002 | US6452852 Semiconductor memory configuration with a refresh logic circuit, and method of refreshing a memory content of the semiconductor memory configuration |
| 09/17/2002 | US6452851 Semiconductor integrated circuit device |
| 09/17/2002 | US6452850 Read amplifier subcircuit for a DRAM memory |
| 09/17/2002 | US6452849 Semiconductor device with test mode for performing efficient calibration of measuring apparatus |
| 09/17/2002 | US6452844 Semiconductor storage device having redundancy circuit for replacement of defect cells under tests |
| 09/17/2002 | US6452842 Device and method for supplying current to a semiconductor memory to support a boosted voltage within the memory during testing |
| 09/17/2002 | US6452841 Dynamic random access memory device and corresponding reading process |
| 09/17/2002 | US6452839 Method for erasing data from a single electron resistor memory |
| 09/17/2002 | US6452838 Nonvolatile memory system, semiconductor memory and writing method |
| 09/17/2002 | US6452834 2T dual-port DRAM in a pure logic process with non-destructive read capability |
| 09/17/2002 | US6452833 Semiconductor memory device |
| 09/17/2002 | US6452832 DRAM circuit and method of controlling the same |
| 09/17/2002 | US6452831 Single electron resistor memory device and method |
| 09/17/2002 | US6452830 Memory configuration including a plurality of resistive ferroelectric memory cells |
| 09/17/2002 | US6452829 Ferroelectric memory device |
| 09/17/2002 | US6452828 Dynamic random access memory (DRAM) having a structure for emplying a word line low voltage |
| 09/17/2002 | US6452825 256 meg dynamic random access memory having a programmable multiplexor |
| 09/17/2002 | US6452824 Semiconductor memory device |
| 09/17/2002 | US6452823 Non-volatile magnetic cache memory and method of use |
| 09/17/2002 | US6452764 Limiting magnetoresistive electrical interaction to a preferred portion of a magnetic region in magnetic devices |
| 09/17/2002 | US6452437 Voltage generator for compensating for temperature dependency of memory cell current |
| 09/17/2002 | US6452432 Signal processing circuits having a pair of delay locked loop (DLL) circuits for adjusting a duty-cycle of a periodic digital signal and methods of operating same |
| 09/17/2002 | US6452269 Semiconductor integrated circuit having power supply pin |
| 09/17/2002 | US6452240 Spin valves; magnetic tunnel junctions used in high speed magnetic random access memory; free magnetic region comprising an alloy of at least one transition metal and two metals chosen from nickel, cobalt and iron |
| 09/17/2002 | US6452239 High-efficiency miniature magnetic integrated circuit structures |
| 09/17/2002 | US6451942 Substrates carrying polymers of linked sandwich coordination compounds and methods of use thereof |
| 09/17/2002 | US6451216 Method of manufacture of a thermal actuated ink jet printer |
| 09/14/2002 | CA2376902A1 Sram emulator |
| 09/14/2002 | CA2340985A1 Interleaved wordline architecture |
| 09/14/2002 | CA2340804A1 Sram emulator |
| 09/12/2002 | WO2002071477A1 Single transistor rare earth manganite ferroelectric nonvolatile memory cell |
| 09/12/2002 | WO2002071448A2 Single transistor ferroelectric memory cell |
| 09/12/2002 | WO2002071410A2 Higher program threshold voltage and faster programming rates based on improved erase methods |
| 09/12/2002 | US20020129298 Method of and apparatus for testing CPU built-in RAM mixed LSI |
| 09/12/2002 | US20020129219 Method and device for sequential readout of a memory with address jump |
| 09/12/2002 | US20020128865 Personal medical database device |
| 09/12/2002 | US20020127801 Nonvolatile ferroelectric memory and method for fabricating the same |