| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 10/01/2002 | US6459329 Power supply auxiliary circuit |
| 10/01/2002 | US6459327 Feedback controlled substrate bias generator |
| 10/01/2002 | US6459317 Sense amplifier flip-flop |
| 10/01/2002 | US6459301 Semiconductor circuit device having active and standby states |
| 10/01/2002 | US6459118 NAND type nonvolatile ferroelectric memory cell |
| 10/01/2002 | US6459110 Semiconductor storage element |
| 10/01/2002 | US6458644 Data bus architecture for integrated circuit devices having embedded dynamic random access memory (DRAM) with a large aspect ratio providing reduced capacitance and power requirements |
| 09/30/2002 | CA2379896A1 Reference cells with integration capacitor |
| 09/30/2002 | CA2379593A1 Ram having dynamically switchable access modes |
| 09/30/2002 | CA2342517A1 Dram cell having increased data retention time |
| 09/30/2002 | CA2342516A1 Dual storage mode dram architecture |
| 09/30/2002 | CA2342508A1 Reference cells with integration capacitor |
| 09/26/2002 | WO2002075926A2 Antifuse reroute of dies |
| 09/26/2002 | WO2002075818A2 Inductive storage capacitor |
| 09/26/2002 | WO2002059898A3 Mram arrangement |
| 09/26/2002 | WO2002058072A3 Dynamic dram refresh rate adjustment based on cell leakage monitoring |
| 09/26/2002 | WO2001084643A3 Method for producing magnetic tunnel contacts, and such a magnetic tunnel contact |
| 09/26/2002 | US20020138690 System and method for performing a partial DRAM refresh |
| 09/26/2002 | US20020138689 Memory device with receives write masking information |
| 09/26/2002 | US20020138688 Memory array with dual wordline operation |
| 09/26/2002 | US20020138243 Semiconductor integrated circuit device |
| 09/26/2002 | US20020137286 Dual floating gate programmable read only memory cell structure and method for its fabrication and operation |
| 09/26/2002 | US20020136243 Method and device for data transfer |
| 09/26/2002 | US20020136081 Semiconductor integrated circuit device |
| 09/26/2002 | US20020136079 Semiconductor memory device and information processing system |
| 09/26/2002 | US20020136077 Semiconductor memory with refresh and method for operating the semiconductor memory |
| 09/26/2002 | US20020136075 Dynamic dram refresh rate adjustment based on cell leakage monitoring |
| 09/26/2002 | US20020136074 Semiconductor device |
| 09/26/2002 | US20020136072 Hierarchical bitline dram architecture system |
| 09/26/2002 | US20020136070 Semiconductor memory device adopting redundancy system |
| 09/26/2002 | US20020136056 Nonvolatile memory system, semiconductor memory, and writing method |
| 09/26/2002 | US20020136055 Nonvolatile semiconductor memory device which stores multi-value information |
| 09/26/2002 | US20020136054 Memory device with multi-level storage cells and apparatuses, systems and methods including same |
| 09/26/2002 | US20020136053 Non-volatile memory device |
| 09/26/2002 | US20020136052 Programmable memory device |
| 09/26/2002 | US20020136051 Small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays |
| 09/26/2002 | US20020136050 Method of programming a memory device |
| 09/26/2002 | US20020136049 Method for sensing data stored in a ferroelectric random access memory device |
| 09/26/2002 | US20020136044 Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency |
| 09/26/2002 | US20020135955 Giant magneto-resistive effect element, magneto-resistive effect type head, thin-film magnetic memory and thin-film magnetic sensor |
| 09/26/2002 | US20020135948 Magnetoresistive effect element, its Manufacturing method, magnetic head, magnetic reproducing apparatus, and magnetic memory |
| 09/26/2002 | US20020135501 Memory device and method having data path with multiple prefetch I/O configurations |
| 09/26/2002 | US20020135394 Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode |
| 09/26/2002 | US20020135027 Semiconductor device, memory system and electronic apparatus |
| 09/26/2002 | US20020135026 Semiconductor device, memory system and electronic apparatus |
| 09/26/2002 | US20020135018 Thin film magnetic memory device writing data of a plurality of bits in parallel |
| 09/26/2002 | US20020135007 Semiconductor device and method of fabricating the same |
| 09/26/2002 | US20020134997 Semiconductor device |
| 09/26/2002 | US20020134996 Information processing structures |
| 09/26/2002 | US20020134994 Memory configuration |
| 09/26/2002 | DE10114280A1 Semiconducting memory with refresh has adiabatic amplifier controlled by output signal from read amplifier to write signal read from memory cell back into memory cell amplified |
| 09/26/2002 | DE10112281A1 Leseverstärkeranordnung für eine Halbleiterspeichereinrichtung Sense amplifier configuration for a semiconductor memory device |
| 09/25/2002 | EP1244144A1 Nonvolatile memory and method of driving nonvolatile memory |
| 09/25/2002 | EP1244118A2 Magnetoresistive element and MRAM using the same |
| 09/25/2002 | EP1244117A2 Magnetoresistive element, memory element using the magnetorestistive element, and recording/reproduction method for the memory element |
| 09/25/2002 | EP1244110A2 Protocol for communication with dynamic memory |
| 09/25/2002 | EP1012845B1 Method and apparatus for local control signal generation in a memory device |
| 09/25/2002 | EP0847582B1 Memory system having programmable control parameters |
| 09/25/2002 | EP0654169B1 Cubic metal oxide thin film epitaxially grown on silicon |
| 09/25/2002 | CN1371175A Command input circuit with command acquisition unit |
| 09/25/2002 | CN1371130A Semiconductor memory unit |
| 09/25/2002 | CN1371099A Self-analyzing semiconductor IC unit capable of carrying out redundant replacement with installed memory circuits |
| 09/24/2002 | US6456563 Semiconductor memory device that operates in sychronization with a clock signal |
| 09/24/2002 | US6456561 Synchronous semiconductor memory device |
| 09/24/2002 | US6456560 Semiconductor integrated circuit device with test interface circuit for performing test on embedded memory from outside |
| 09/24/2002 | US6456559 Semiconductor integrated circuit |
| 09/24/2002 | US6456558 Column decoding apparatus for use in a semiconductor memory device |
| 09/24/2002 | US6456555 Voltage detecting circuit for semiconductor memory device |
| 09/24/2002 | US6456553 Circuit configuration for switching over a receiver circuit in particular in DRAM memories and DRAM memory having the circuit configuration |
| 09/24/2002 | US6456551 Semiconductor memory device having prefetch operation mode and data transfer method for reducing the number of main data lines |
| 09/24/2002 | US6456549 Sense amplifier circuit and semiconductor storage device |
| 09/24/2002 | US6456548 Sense amplifier circuit and semiconductor storage device |
| 09/24/2002 | US6456545 Method and apparatus for data transmission and reception |
| 09/24/2002 | US6456536 Method of programming a non-volatile memory cell using a substrate bias |
| 09/24/2002 | US6456533 Higher program VT and faster programming rates based on improved erase methods |
| 09/24/2002 | US6456532 Semiconductor memory device |
| 09/24/2002 | US6456531 Method of drain avalanche programming of a non-volatile memory cell |
| 09/24/2002 | US6456528 Selective operation of a multi-state non-volatile memory system in a binary mode |
| 09/24/2002 | US6456527 Nonvolatile multilevel memory and reading method thereof |
| 09/24/2002 | US6456526 Non-volatile memory device operation in response to two different types of read commands and a write command which includes write verification |
| 09/24/2002 | US6456525 Short-tolerant resistive cross point array |
| 09/24/2002 | US6456524 Hybrid resistive cross point memory cell arrays and methods of making the same |
| 09/24/2002 | US6456523 Ferromagnetic double quantum well tunnel magneto-resistance device |
| 09/24/2002 | US6456522 Integrated memory having memory cells and buffer capacitors |
| 09/24/2002 | US6456521 Hierarchical bitline DRAM architecture system |
| 09/24/2002 | US6456520 Semiconductor memory and method for driving the same |
| 09/24/2002 | US6456519 Circuit and method for asynchronously accessing a ferroelectric memory device |
| 09/24/2002 | US6456517 System having memory devices operable in a common interface |
| 09/24/2002 | US6456513 Voltage conversion circuit and control circuit therefor |
| 09/24/2002 | US6456152 Charge pump with improved reliability |
| 09/24/2002 | US6456129 Internal clock signal generator |
| 09/24/2002 | US6456124 Method and apparatus for controlling impedance of an off-chip driver circuit |
| 09/24/2002 | US6456119 Decoding apparatus |
| 09/24/2002 | US6456118 Decoder circuit |
| 09/24/2002 | US6456098 Method of testing memory cells with a hysteresis curve |
| 09/24/2002 | US6455899 Semiconductor memory device having improved pattern of layers and compact dimensions |
| 09/24/2002 | US6455392 Integrated resistor having aligned body and contact and method for forming the same |
| 09/24/2002 | US6455367 Method of making high density semiconductor memory |
| 09/22/2002 | CA2378560A1 Method and apparatus for generating and controlling spin propagation using one or more coherent light beams |
| 09/19/2002 | WO2002073658A2 Yield and speed enhancement of semiconductor integrated circuits using post-fabrication transistor mismatch compensation circuitry |