Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
10/2002
10/24/2002US20020153525 Semiconductor device with process monitor circuit and test method thereof
10/24/2002US20020153160 Electronic device and method for fabricating an electronic device
10/24/2002DE10201865A1 Speichervorrichtung mit einer Vorauslesedaten-Ordnung, die in einer Vorauslese-Datenpfadlogik verteilt ist, sowie Schaltung und Verfahren zum Ordnen von Vorauslesedaten Memory device having a prefetch data order, which is distributed in a prefetch data path logic, and circuit and method for arranging prefetch data
10/24/2002DE10160089A1 Halbleiterspeichervorrichtung A semiconductor memory device
10/24/2002DE10135573A1 Transistor arrangement as sense amplifier has at least one second double row of paired transistors of first or second type; rows are offset and gaps of at least one row are left
10/24/2002DE10118197A1 Integrated magnetoresistive semiconducting memory arrangement has third conductor plane occupied by write selection lines and spatially and electrically separate from first two read planes
10/24/2002DE10118196A1 Operating MRAM semiconducting memory involves subjecting memory cell to transient reversible magnetic change while reading information, comparing changed/original current signals
10/23/2002EP1251570A2 Method of fabricating magnetic random access memory based on tunnel magnetroresistance effect
10/23/2002EP1251523A1 Method and circuit for timing dynamic reading of a memory cell with control of the integration time
10/23/2002EP1251522A2 Semiconductor memory device
10/23/2002EP1251521A1 A dynamic random access memory device externally functionally equivalent to a static random access memory
10/23/2002EP1251520A2 Random access memory
10/23/2002EP1251519A1 Semiconductor memory device using magneto resistive element and method of manufacturing the same
10/23/2002EP1251518A2 Method and apparatus for high-speed read operation in semiconductor memory
10/23/2002EP1099223B1 Storage assembly comprised of a plurality of resistive ferroelectric storage cells
10/23/2002EP1019910B1 Selective power distribution circuit for an integrated circuit
10/23/2002CN1376299A Polyvalent, magnetoresistive write/read memory and method for writing and reading a memory of this type
10/23/2002CN1376298A Memory devices
10/23/2002CN1375873A High speed and high-capacity flash solid memory structure and manufacture process
10/23/2002CN1375831A Memory updating system
10/23/2002CN1375830A Semiconductor storage apparatus
10/23/2002CN1375829A Semiconductor storage adopting reductant mode
10/23/2002CN1093339C 半导体器件及其输出电路 Semiconductor device and an output circuit
10/23/2002CN1093306C High-speed buffer storage using a pseudo static four-transistor memory cell
10/22/2002US6470475 Synthesizable synchronous static RAM
10/22/2002US6470467 Synchronous semiconductor memory device capable of performing operation test at high speed while reducing burden on tester
10/22/2002US6470465 Parallel test circuit of semiconductor memory device
10/22/2002US6469954 Device and method for reducing idle cycles in a semiconductor memory device
10/22/2002US6469952 Semiconductor memory device capable of reducing power supply voltage in a DRAM's word driver
10/22/2002US6469950 Static memory cell having independent data holding voltage
10/22/2002US6469948 Semiconductor device
10/22/2002US6469947 Semiconductor memory device having regions with independent word lines alternately selected for refresh operation
10/22/2002US6469941 Apparatus and method for pumping memory cells in a memory
10/22/2002US6469940 Memory access method and system for writing and reading SDRAM
10/22/2002US6469937 Current sense amplifier circuit
10/22/2002US6469931 Method for increasing information content in a computer memory
10/22/2002US6469927 Magnetoresistive trimming of GMR circuits
10/22/2002US6469926 Magnetic element with an improved magnetoresistance ratio and fabricating method thereof
10/22/2002US6469925 Memory cell with improved retention time
10/22/2002US6469924 Memory architecture with refresh and sense amplifiers
10/22/2002US6469923 Semiconductor device with programming capacitance element
10/22/2002US6469573 Semiconductor integrated circuit
10/22/2002US6469571 Charge pump with charge equalization for improved efficiency
10/22/2002US6469568 Metal oxide semiconductor transistor circuit and semiconductor integrated circuit using the same
10/22/2002US6469565 Duty cycle adaptive data output buffer
10/22/2002US6469557 Semiconductor integrated circuit and delayed clock signal generation method
10/22/2002US6469546 Sense amplifier circuit
10/22/2002US6469355 Configuration for voltage buffering in a dynamic memory using CMOS technology
10/22/2002US6469343 Multi-level type nonvolatile semiconductor memory device
10/22/2002US6468855 Reduced topography DRAM cell fabricated using a modified logic process and method for operating same
10/22/2002US6468809 Which responds to radial fringing field; electroconductivity; ferromagnetism; immunoassay; dna hybridization assay
10/17/2002WO2002082510A1 Single transistor rare earth manganite ferroelectric nonvolatile memory cell
10/17/2002WO2002082504A2 Data restore in thyristor-based memory
10/17/2002WO2002082460A1 Semiconductor non-volatile storage device
10/17/2002WO2002082456A1 Device and method for using complementary bits in a memory array
10/17/2002WO2002082455A1 Dram and dram refresh method
10/17/2002WO2002082454A1 Semiconductor storage device
10/17/2002WO2002082453A1 Dynamic data restore in thyristor-based memory device
10/17/2002WO2002082452A2 Microelectronic device, structure, and system, including a memory structure having a variable programmable property and method of forming the same
10/17/2002WO2002082451A1 A non-volatile memory device having high speed page mode operation
10/17/2002WO2002082450A1 Method for operating a semiconductor memory at a data transmission rate which is twice as fast
10/17/2002WO2002067266A3 Method for writing into magnetoresistive memory cells and magnetoresistive memory which can be written into according to said method
10/17/2002WO2002048822A3 Ram memory based on nanotechnology, capable, among other things, of replacing the hard disk in computers
10/17/2002WO2002039455A8 Mram arrangement with selection transistors of large channel width
10/17/2002US20020152442 Error correction code circuits
10/17/2002US20020152351 Memory control circuit
10/17/2002US20020151173 Single electron resistor memory device and method
10/17/2002US20020151172 Single electron resistor memory device and method
10/17/2002US20020149993 Fast cycle RAM and data readout method therefor
10/17/2002US20020149992 Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devices
10/17/2002US20020149991 Test circuit for testing semiconductor memory
10/17/2002US20020149990 Semiconductor memory device having asymmetric data paths
10/17/2002US20020149987 Adjustable circuits for analog or multi-level memory
10/17/2002US20020149986 Dynamic refresh that changes the physical storage locations of data in flash memory
10/17/2002US20020149985 Semiconductor memory device having refreshing function
10/17/2002US20020149973 Semiconductor memory device
10/17/2002US20020149972 Analog-to-digital converter for monitoring vddq and dynamically updating programmable vref when using high-frequency receiver and driver circuits for commercial memory
10/17/2002US20020149971 Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other
10/17/2002US20020149966 Device and method for supplying current to a semiconductor memory to support a boosted voltage within the memory during testing
10/17/2002US20020149965 Method and circuit for dynamic reading of a memory cell at low supply voltage and with low output dynamics
10/17/2002US20020149964 Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell
10/17/2002US20020149963 Programming method for a multilevel memory cell
10/17/2002US20020149962 Magnetic random access memory
10/17/2002US20020149961 Semiconductor memory device
10/17/2002US20020149960 Memory device with prefetched data ordering distributed in prefetched data path logic, circuit, and method of ordering prefetched data
10/17/2002US20020149957 256 meg dynamic random access memeory
10/17/2002US20020149647 Pusher actuation in a printhead chip for an inkjet printhead
10/17/2002US20020149560 Graphics controller integrated circuit without memory interface
10/17/2002US20020149391 Antifuse reroute of dies
10/17/2002DE10207312A1 Ferroelektrische nichtflüchtige Logikelemente A ferroelectric nonvolatile logic elements
10/17/2002DE10156722A1 Halbleiterspeichervorrichtung mit Redundanzsystem A semiconductor memory device with redundant system
10/17/2002DE10117614A1 Verfahren zum Betreiben eines Halbleiterspeichers mit doppelter Datenübertragungsrate A method of operating a semiconductor memory device with double data rate
10/17/2002DE10116327A1 Schaltungsanordnung zum Steuern der Wortleitungen einer Speichermatrix Circuitry for controlling the word lines of a memory matrix
10/17/2002DE10116325A1 Circuit for memory, especially DRAM, has read amplifier that actively places second bit line adjacent to first bit line at defined potential while first bit line is being read out.
10/17/2002DE10115291C1 Dynamic semiconductor memory in personal computer, includes controller which is programmed to refresh memory bank by resetting all word lines and to activate word lines
10/16/2002EP1249842A1 Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude
10/16/2002EP1249841A1 Reading circuit and method for a multilevel non volatile memory
10/16/2002EP1249021A1 Substrates carrying polymers of linked sandwich coordination compounds and methods of use thereof
10/16/2002EP1249020A2 Decoder circuit
10/16/2002EP1078372A4 High-efficiency miniature magnetic integrated circuit structures
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