Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
12/2002
12/12/2002US20020186609 Semiconductor memory device with reduced power consumption during refresh operation
12/12/2002US20020186608 High frequency range four bit prefetch output data path
12/12/2002US20020186607 Sense amplifier and architecture for open digit arrays
12/12/2002US20020186604 Fail repair circuit of nonvolatile ferroelectric memory device and method for repairing the same
12/12/2002US20020186600 Column repair circuit and method of using nonvolatile ferroelectric memory device
12/12/2002US20020186598 Semiconductor circuit device with improved special mode
12/12/2002US20020186596 Semiconductor device with data output circuit having slew rate adjustable
12/12/2002US20020186592 Reading circuit and method for a multilevel non-volatile memory
12/12/2002US20020186591 Semiconductor memory device having memory cell arrays capable of accomplishing random access
12/12/2002US20020186587 Electrically alterable non-volatile memory with n-bits per cell
12/12/2002US20020186584 High-efficiency miniature magnetic integrated circuit structures
12/12/2002US20020186583 Recessed magnetic storage element and method of formation
12/12/2002US20020186582 Cladded read conductor for a pinned-on-the-fly soft reference layer
12/12/2002US20020186581 Semiconductor memory device with memory cells operated by boosted voltage
12/12/2002US20020186580 Converting volatile memory to non-volatile memory
12/12/2002US20020186579 Static RAM with optimized timing of driving control signal for sense amplifier
12/12/2002US20020186574 Voltage booster circuit and semiconductor device for incorporating same
12/12/2002US20020186071 Semiconductor integrated circuit device including a substrate bias controller and a current limiting circuit
12/12/2002US20020186064 Delay circuit having low operating environment dependency
12/12/2002US20020186051 Sense amplifier with improved latching
12/12/2002US20020186040 Semiconductor logic circuit device of low current consumption
12/12/2002US20020185674 Nonvolatile semiconductor storage device and production method therefor
12/12/2002US20020185663 Method of making loadless four-transistor mrmory cell with different gate insulation thicknesses for n-channel drive transistors and p-channel access transistors
12/12/2002US20020185337 Semiconductor device with non-volatile memory and random access memory
12/12/2002DE10225398A1 Halbleiterspeichervorrichtung mit Speicherzellenarrays, die zum Durchführen eines wahlfreien Zugriffs in der Lage ist A semiconductor memory device comprising memory cell arrays, which is for performing a random access in a position
12/12/2002DE10220561A1 Negative voltage generator for semiconductor memory device, includes two negative charge pump controlled by precharge signal
12/12/2002DE10159368A1 Halbleiterspeichervorrichtung mit verringertem Leistungsverbrauch während der Auffrischoperation A semiconductor memory device with reduced power consumption during the refresh operation
12/12/2002DE10158310A1 Schaltung und Verfahren zur Spaltenreparatur bei einem nichtflüchtigen ferroelektrischen Speicher Circuit and method for column repair in a non-volatile ferroelectric memory
12/12/2002DE10128264A1 Digital magnetic memory cell device e.g. for read- and/or write-operations, has magnetic layer arranged remote from anti-ferromagnetic layer
12/12/2002DE10128154A1 Digital magnetic storage cell arrangement used for reading and writing operations comprises a soft magnetic reading and/or writing layer system, and a hard magnetic reference layer system formed as an AAF system
12/12/2002DE10125800A1 Speicherbaustein mit einer Speicherzelle und Verfahren zur Herstellung eines Speicherbausteins Memory device having a memory cell and method for manufacturing a memory device
12/12/2002DE10125022A1 Dynamischer Speicher und Verfahren zum Testen eines dynamischen Speichers Dynamic memory and method for testing a dynamic memory
12/12/2002DE10119125C1 Verfahren zum Vergleich der Adresse eines Speicherzugriffs mit einer bereits bekannten Adresse einer fehlerhaften Speicherzelle A method for comparing the address of a memory access to a known address of a defective memory cell
12/11/2002EP1265289A2 Electrically erasable and programmable memory device
12/11/2002EP1265251A2 Sensing methodology for a 1T/1C ferroelectric memory
12/11/2002EP1265250A2 Ferroelectric memory
12/11/2002EP1265249A2 Magneto-resistance effect film and memory using it
12/11/2002EP1265247A1 A programmable delay line and corresponding memory
12/11/2002EP1264190A1 Circuit and method for evaluating capacitors in matrices
12/11/2002EP1166274B1 Device for weighting the cell resistances in a magnetoresistive memory
12/11/2002EP1163676B1 Storage cell array and method for the production thereof
12/11/2002CN1384545A Semiconductor memory device and its manufacture
12/11/2002CN1384506A Automatic partial-array updating system and method for semiconductor memory
12/11/2002CN1384505A Low-voltage control method and device
12/11/2002CN1384504A Low-voltage conrol method and device
12/11/2002CN1384503A Magnetic resistance element, memory unit with the element and memory constituted by the memory units
12/11/2002CN1096147C Semiconductor integral circuit with reduced current leakage and high speed
12/11/2002CN1096118C Intermediate potential generation circuit
12/11/2002CN1096083C Semi-conductor memory device
12/11/2002CN1096081C Non-losable semi-conductor storage device
12/11/2002CN1096080C Semiconductor memory device having dual word line configuration
12/10/2002USRE37930 DRAM including an address space divided into individual blocks having memory cells activated by row address signals
12/10/2002US6493855 Flexible cache architecture using modular arrays
12/10/2002US6493836 Method and apparatus for scheduling and using memory calibrations to reduce memory errors in high speed memory devices
12/10/2002US6493829 Semiconductor device enable to output a counter value of an internal clock generation in a test mode
12/10/2002US6493789 Memory device which receives write masking and automatic precharge information
12/10/2002US6493394 Signal transmission system for transmitting signals between lsi chips, receiver circuit for use in the signal transmission system, and semiconductor memory device applying the signal transmission system
12/10/2002US6493286 tRCD margin
12/10/2002US6493284 Semiconductor memory device having hierarchical wordline structure
12/10/2002US6493283 Architecture, method (s) and circuitry for low power memories
12/10/2002US6493282 Semiconductor integrated circuit
12/10/2002US6493281 Semiconductor device, method for refreshing the same, system memory, and electronics apparatus
12/10/2002US6493279 Semiconductor device capable of simple measurement of oscillation frequency
12/10/2002US6493274 Data transfer circuit and semiconductor integrated circuit having the same
12/10/2002US6493273 Semiconductor memory having electrically erasable and programmable nonvolatile semiconductor memory cells
12/10/2002US6493265 Nonvolatile semiconductor memory device
12/10/2002US6493260 Nonvolatile memory device, having parts with different access time, reliability, and capacity
12/10/2002US6493259 Pulse write techniques for magneto-resistive memories
12/10/2002US6493258 Magneto-resistive memory array
12/10/2002US6493256 Semiconductor memory device
12/10/2002US6493254 Current leakage reduction for loaded bit-lines in on-chip memory structures
12/10/2002US6493253 DRAM memory cell
12/10/2002US6493252 Selective device coupling
12/10/2002US6493251 Ferroelectric memory device
12/10/2002US6492863 Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor
12/10/2002US6492850 Semiconductor integrated circuit and method for generating internal supply voltage in semiconductor integrated circuit
12/10/2002US6492721 High-voltage signal detecting circuit
12/10/2002US6492231 Method of making triple self-aligned split-gate non-volatile memory device
12/10/2002US6492228 Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
12/10/2002US6492222 Lead zirconate titanate dielectric situated between elec-trodes; hardmasking with refractory nitride; removing portion of hardmask and ferroelectric material using chlorine, oxygen and fluorine bearing compounds
12/10/2002US6491833 Method of manufacture of a dual chamber single vertical actuator ink jet printer
12/05/2002WO2002043067A3 Integrated memory with an arrangement of non-volatile memory cells and method for the production and operation of an integrated memory
12/05/2002US20020184592 Semiconductor memory device
12/05/2002US20020184454 Memory access device
12/05/2002US20020184438 Memory control system
12/05/2002US20020184437 Memory architecture for supporting concurrent access of different types
12/05/2002US20020182800 Semiconductor memory device
12/05/2002US20020182756 Nonvolatile ferroelectric memory and method for fabricating the same
12/05/2002US20020182754 Semiconductor memory device and manufacturing method thereof
12/05/2002US20020182442 A magnetic film whose easy axis of magnetization is inclined from a direction perpendicular to the film surface is formed at a position where the magnetic film contacts the perpendicular magnetization film
12/05/2002US20020181318 Semiconductor storage unit
12/05/2002US20020181317 Trcd margin
12/05/2002US20020181316 System to set burst mode in a device
12/05/2002US20020181308 Information storage apparatus, information storage method, recording medium and program
12/05/2002US20020181307 Single bitline direct sensing architecture for high speed memory device
12/05/2002US20020181306 Method for multilevel DRAM sensing
12/05/2002US20020181305 Trcd margin
12/05/2002US20020181301 Semiconductor storage and method for testing the same
12/05/2002US20020181300 Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts
12/05/2002US20020181295 TRCD margin
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