| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 06/13/2002 | US20020071321 System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories |
| 06/13/2002 | US20020071319 Method and apparatus for data transmission and reception |
| 06/13/2002 | US20020071318 Semiconductor device |
| 06/13/2002 | US20020071317 Integrated memory having memory cells and reference cells, and corresponding operating method |
| 06/13/2002 | US20020071315 Nonvolatile memory having embedded word lines |
| 06/13/2002 | US20020071313 Non-volatile semiconductor memory device |
| 06/13/2002 | US20020071312 Semiconductor memory device |
| 06/13/2002 | US20020071309 Substitute specification |
| 06/13/2002 | US20020071308 Semiconductor memory device having memory cells each capable of storing three or more values |
| 06/13/2002 | US20020071307 Method and circuit for programming a multilevel non-volatile memory |
| 06/13/2002 | US20020071306 Device for evaluating cell resistances in a magnetoresistive memory |
| 06/13/2002 | US20020071304 Nonvolatile ferroelectric memory having shunt lines |
| 06/13/2002 | US20020071303 Configuration and method for increasing the retention time and the storage security in a ferroelectric or ferromagnetic semiconductor memory |
| 06/13/2002 | US20020071302 Semiconductor memory with multistage local sense amplifier |
| 06/13/2002 | US20020071104 Image sensing apparatus including a microcontroller |
| 06/13/2002 | US20020071066 Compact display assembly |
| 06/13/2002 | US20020070776 Semiconductor device capable of immediately recovering from erroneous state to normal state |
| 06/13/2002 | US20020070762 Amplifier for use in semiconductor integrated circuits |
| 06/13/2002 | US20020070396 Ferroelectric memory having electromagnetic wave shield structure |
| 06/13/2002 | DE10146825A1 Programmierbare Impedanzsteuerschaltung Programmable impedance control circuit |
| 06/13/2002 | DE10062570C1 Read and write control circuit for magnetoresistive random-access memory has read/write amplifier pairs at opposite ends of bit lines |
| 06/13/2002 | DE10059182A1 Schaltungsanordnung zum zerstörungsfreien, selbstnormierenden Auslesen von MRAM-Speicherzellen Circuit arrangement for non-destructive, selbstnormierenden reading MRAM memory cells |
| 06/13/2002 | DE10058966A1 Charging memory cells involves selecting memory cells and carrying out refresh process only for selected memory cells; memory cells can be selected by area of memory |
| 06/13/2002 | DE10058965A1 RAM memory has at least some cells with additional device for activation by forced control voltage different from normal control voltage to impose defined logical state on memory cells |
| 06/13/2002 | DE10058398A1 Integrated semiconductor memory device e.g. dynamic random access memory (DRAM), memory cells are accessed by activating the word line |
| 06/13/2002 | DE10058047A1 Integrierter Speicher mit einer Anordnung von nicht-flüchtigen Speicherzellen und Verfahren zur Herstellung und zum Betrieb des integrierten Speichers Integrated memory with an arrangement of non-volatile memory cells and methods of manufacturing and operating the integrated memory |
| 06/13/2002 | DE10056283A1 Artificial neuron for artificial neural network, has transistor with several inputs connected to first transistor input in parallel via resistance elements containing material ensuring a varistor effect |
| 06/12/2002 | EP1213745A1 Method of producing a ferroelectric memory and memory device |
| 06/12/2002 | CN1353460A Data storage possessing sereral storage unit |
| 06/12/2002 | CN1353422A Magnetic storage equipment containing storage element exhibiting strong magnetic tunnel effect |
| 06/12/2002 | CN1353421A Film magnetic body storage possessing highly integrated storage array |
| 06/11/2002 | US6404699 Integrated circuit having a command decoder |
| 06/11/2002 | US6404697 Data output device for synchronous memory device |
| 06/11/2002 | US6404696 Random access memory with divided memory banks and data read/write architecture therefor |
| 06/11/2002 | US6404695 Semiconductor memory device including a plurality of memory blocks arranged in rows and columns |
| 06/11/2002 | US6404693 Integrated circuit memory devices that select sub-array blocks and input/output line pairs based on input/output bandwidth, and methods of controlling same |
| 06/11/2002 | US6404692 Semiconductor memory |
| 06/11/2002 | US6404690 Refresh drive circuit for a DRAM |
| 06/11/2002 | US6404689 Method and structure for hiding a refresh operation in a DRAM having an interlocked pipeline |
| 06/11/2002 | US6404688 Semiconductor memory device having a self-refresh operation |
| 06/11/2002 | US6404687 Semiconductor integrated circuit having a self-refresh function |
| 06/11/2002 | US6404685 Equilibrate circuit for dynamic plate sensing memories |
| 06/11/2002 | US6404679 Multiple level floating-gate memory |
| 06/11/2002 | US6404678 Source and drain sensing |
| 06/11/2002 | US6404675 Electrically alterable non-volatile memory with n-bits per cell |
| 06/11/2002 | US6404674 Cladded read-write conductor for a pinned-on-the-fly soft reference layer |
| 06/11/2002 | US6404673 Magnetic memory device and method of reading data in magnetic memory device |
| 06/11/2002 | US6404672 Magnetic element and magnetic memory device |
| 06/11/2002 | US6404671 Data-dependent field compensation for writing magnetic random access memories |
| 06/11/2002 | US6404670 Multiple ports memory-cell structure |
| 06/11/2002 | US6404669 Reduced leakage DRAM storage unit |
| 06/11/2002 | US6404668 Memory configuration including a plurality of resistive ferroelectric memory cells |
| 06/11/2002 | US6404667 2T-1C ferroelectric random access memory and operation method thereof |
| 06/11/2002 | US6404663 Semiconductor integrated circuit having testing mode for modifying operation timing |
| 06/11/2002 | US6404661 Semiconductor storage device having arrangement for controlling activation of sense amplifiers |
| 06/11/2002 | US6404258 Delay circuit having low operating environment dependency |
| 06/11/2002 | US6404254 Latch circuit and semiconductor integrated circuit having the latch circuit with control signal having a large voltage amplitude |
| 06/11/2002 | US6404250 On-chip circuits for high speed memory testing with a slow memory tester |
| 06/11/2002 | US6404233 Method and apparatus for logic circuit transition detection |
| 06/11/2002 | US6404221 Threshold invariant voltage detecting device |
| 06/11/2002 | US6404178 Power supply circuit capable of supplying a stable power supply potential even to a load consuming rapidly changing current |
| 06/06/2002 | WO2002045093A1 Semiconductor memory device and address conversion circuit |
| 06/06/2002 | WO2002045090A2 Circuit for non-destructive, self-normalizing reading-out of mram memory cells |
| 06/06/2002 | WO2002005268A3 All metal giant magnetoresistive memory |
| 06/06/2002 | WO2002001568A3 Dynamic random access memory |
| 06/06/2002 | WO2001071721A3 Method and apparatus for an improved reset and power-on arrangement for a dram generator controller |
| 06/06/2002 | US20020069026 Semiconductor device capable of test mode operation |
| 06/06/2002 | US20020067654 Synchronous memory modules and memory systems with selectable clock termination |
| 06/06/2002 | US20020067651 Charge pump for negative differential resistance transistor |
| 06/06/2002 | US20020067650 Semiconductor memory with built-in cache |
| 06/06/2002 | US20020067649 Semiconductor memory, and memory access method |
| 06/06/2002 | US20020067648 Asynchronous SRAM compatible memory device using DRAM cell and method for driving the same |
| 06/06/2002 | US20020067647 Semiconductor integrated circuit device |
| 06/06/2002 | US20020067644 Wordline driver for ensuring equal stress to wordlines in multi row address disturb test and method of driving the wordline driver |
| 06/06/2002 | US20020067643 Reduced power bit line selection in memory circuits |
| 06/06/2002 | US20020067642 Semiconductor memory |
| 06/06/2002 | US20020067637 Semiconductor memory |
| 06/06/2002 | US20020067635 Wide databus architecture |
| 06/06/2002 | US20020067581 Magnetoresistive device and/or multi-magnetoresistive device |
| 06/06/2002 | US20020067201 Driver timing and circuit technique for a low noise charge pump circuit |
| 06/06/2002 | US20020067197 Phase adjustor for semiconductor integrated circuit |
| 06/06/2002 | US20020066933 Negative differential resistance field effect transistor (NDR-FET) & circuits using the same |
| 06/06/2002 | US20020066915 Method of producing a ferroelectric memory and a memory device |
| 06/06/2002 | DE10129263A1 Non-volatile ferroelectric memory has pulse width generating unit for varying width of reproduction pulse and outputting varied width to word line driver to identify defective cell |
| 06/06/2002 | DE10058782A1 Method for producing a capacitor structure for a memory device fits multiple capacitors on a carrier like a semiconductor substrate with a common contact area. |
| 06/06/2002 | DE10057275C1 Memory cell refreshing device for dynamic random-access memory provides information refresh control signal sequence dependent on maximum storage times of individual memory cells |
| 06/05/2002 | EP1211812A2 A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device |
| 06/05/2002 | EP1211731A2 A symmetric architecture for memory cells having widely spread metal bit lines |
| 06/05/2002 | EP1211692A2 Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell |
| 06/05/2002 | EP1210714A2 High density non-volatile memory device |
| 06/05/2002 | EP1016087B1 Memory location arrangement and its use as a magnetic ram and as an associative memory |
| 06/05/2002 | CN1352808A Electrically programmable memory element with improved contacts |
| 06/05/2002 | CN1352788A Ultrafast magnetization reversal |
| 06/04/2002 | US6401180 Bank history table for improved pre-charge scheduling of random access memory banks |
| 06/04/2002 | US6401167 High performance cost optimized memory |
| 06/04/2002 | US6400643 Semiconductor storage device with suppressed power consumption and reduced recovery time from suspend mode |
| 06/04/2002 | US6400637 Semiconductor memory device |
| 06/04/2002 | US6400636 Address generator for a semiconductor memory |
| 06/04/2002 | US6400635 Memory circuitry for programmable logic integrated circuit devices |
| 06/04/2002 | US6400632 Semiconductor device including a fuse circuit in which the electric current is cut off after blowing so as to prevent voltage fall |