Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
10/2002
10/16/2002EP0766258B1 Dram signal margin test method
10/16/2002EP0601068B1 Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
10/16/2002CN1374691A Method for producing top conductor covering
10/16/2002CN1374663A Storing unit with improved reliability, nonvolatile memory and its controlling method
10/15/2002US6466511 Semiconductor memory having double data rate transfer technique
10/15/2002US6466509 Semiconductor memory device having a column select line transmitting a column select signal
10/15/2002US6466507 DRAM with intermediate storage cache and separate read and write I/O
10/15/2002US6466506 Semiconductor memory device capable of repairing small leak failure
10/15/2002US6466504 Compilable block clear mechanism on per I/O basis for high-speed memory
10/15/2002US6466503 Semiconductor memory with current distributor
10/15/2002US6466502 Semiconductor memory device having switching and memory cell transistors with the memory cell having the lower threshold voltage
10/15/2002US6466501 Semiconductor memory device having sense amplifier and method for driving sense amplifier
10/15/2002US6466499 DRAM sense amplifier having pre-charged transistor body nodes
10/15/2002US6466498 Discontinuity-based memory cell sensing
10/15/2002US6466496 Semiconductor integrated circuit having circuit for data transmission distance measurement and memory processing system with the same
10/15/2002US6466494 Semiconductor integrated circuit device with memory circuit
10/15/2002US6466492 Synchronous semiconductor memory device and method for controlling mask data input circuit
10/15/2002US6466490 Semiconductor memory circuit
10/15/2002US6466489 Use of source/drain asymmetry MOSFET devices in dynamic and analog circuits
10/15/2002US6466488 Reduction of data dependent power supply noise when sensing the state of a memory cell
10/15/2002US6466487 Semiconductor device with impedance controllable output buffer
10/15/2002US6466486 Buffer circuit, and semiconductor device and semiconductor memory device including same
10/15/2002US6466483 Piggyback programming using timing control for multi-level cell flash memory designs
10/15/2002US6466477 Method of stabilizing reference bit of multi-bit memory cell
10/15/2002US6466476 Data coding for multi-bit-per-cell memories having variable numbers of bits per memory cell
10/15/2002US6466475 Uniform magnetic environment for cells in an MRAM array
10/15/2002US6466474 Memory module having a two-transistor memory cell
10/15/2002US6466473 Method and apparatus for increasing signal to sneak ratio in polarizable cross-point matrix memory arrays
10/15/2002US6466471 Low power MRAM memory array
10/15/2002US6466221 Data processing system and image processing system
10/15/2002US6466192 Matrix display apparatus, matrix display control apparatus, and matrix display drive apparatus
10/15/2002US6466077 Semiconductor integrated circuit device including a speed monitor circuit and a substrate bias controller responsive to the speed-monitor circuit
10/15/2002US6466075 Clock signal generator for generating signal with differing phase for an integrated circuit
10/15/2002US6466053 Antifuse reroute of dies
10/15/2002US6465818 Semiconductor memory device capable of performing data writing or erasing operation and data reading operation in parallel
10/15/2002US6465375 Single electron MOSFET memory device and method
10/10/2002WO2002080184A2 On-chip circuits for high speed memory testing with a slow memory tester
10/10/2002WO2002080183A2 Memory cell structural test
10/10/2002WO2002080180A1 Dram and access method
10/10/2002US20020147885 Method for hiding a refresh in a pseudo-static memory
10/10/2002US20020147884 Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM
10/10/2002US20020147877 Synchronous memory device
10/10/2002US20020146025 Arbiter device for multi-port memory and semiconductor device
10/10/2002US20020145936 Semiconductor memory device with single clock signal line
10/10/2002US20020145935 Semiconductor integrated circuit
10/10/2002US20020145934 Method and apparatus for high-speed read operation in semiconductor memory
10/10/2002US20020145930 Semiconductor integrated circuit
10/10/2002US20020145929 Control circuit and semiconductor memory device
10/10/2002US20020145927 Semiconductor integrated circuit device and data-write method thereof
10/10/2002US20020145925 Semiconductor device capable of simple measurement of oscillation frequency
10/10/2002US20020145920 Semiconductor memory device
10/10/2002US20020145918 Architecture and scheme for a non-strobed read sequence
10/10/2002US20020145917 Device and method for using complementary bits in a memory array
10/10/2002US20020145915 Process for making and programming and operating a dual-bit multi-level ballistic flash memory
10/10/2002US20020145914 Process for making and programming and operating a dual-bit multi-level ballistic flash memory
10/10/2002US20020145908 Non-volatile memory device having high speed page mode operation
10/10/2002US20020145905 Nonvolatile solid-state memory and method of driving the same
10/10/2002US20020145904 Inductive storage capacitor
10/10/2002US20020145903 Ferroelectric memory device and method of driving the same
10/10/2002US20020145902 Magnetic memory device and magnetic substrate
10/10/2002US20020145480 Oscillator circuit of internal power generator circuit and control method thereof
10/10/2002US20020145466 Internal power voltage generating circuit of semiconductor device
10/10/2002US20020145447 Semiconductor integrated circuit and method of switching source potential of transistor in semiconductor integrated circuit
10/10/2002US20020145412 Power supply circuit stably supplying power supply potential even to load consuming rapidly changing current and semiconductor memory device with same
10/10/2002US20020145161 Multi-level type nonvolatile semiconductor memory device
10/10/2002DE10115817A1 Integrierter Speicherchip mit einem dynamischen Speicher Built-in memory chip with a dynamic memory
10/10/2002DE10115816A1 Integrierter dynamischer Speicher und Verfahren zum Betrieb eines integrierten dynamischen Speichers Integrated dynamic memory and method of operating a dynamic memory integrated
10/09/2002EP1248298A1 Stitch and select implementation in twin monos array
10/09/2002EP1248273A2 Cladded read conductor for a tunnel junction memory cell
10/09/2002EP1248267A2 Semiconductor memory device and information processing system
10/09/2002EP1248266A2 Control circuit and semiconductor memory device
10/09/2002EP1248265A2 Magnetic memory cell
10/09/2002EP1248264A2 Magnetoresistive element, memory element having the magnetoresistive element, and memory using the memory element
10/09/2002EP1248262A1 Method for writing data into a semiconductor memory device and semiconductor memory therefor
10/09/2002EP1248261A2 Random and rapid DRAM memory access management method
10/09/2002CN1373479A High data read-out allowance memory for storing data using change of resistance quantity
10/09/2002CN1092387C Semiconductor memory device capable of simultaneously designating multibit test mode and special test mode
10/09/2002CN1092386C Semiconductor storage device
10/09/2002CN1092385C Semiconductor memory device for block access applications
10/09/2002CN1092335C Voltage detecting circuit, power on/off resetting circuit and semiconductor device
10/08/2002US6463558 Semiconductor memory device
10/08/2002US6463424 Association unit, association apparatus and method for the same
10/08/2002US6463008 Semiconductor integrated circuit device
10/08/2002US6463007 Synchronous semiconductor memory device
10/08/2002US6463005 Semiconductor memory device
10/08/2002US6463002 Refresh-type memory with zero write recovery time and no maximum cycle time
10/08/2002US6463001 Circuit and method for merging refresh and access operations for a memory device
10/08/2002US6462999 Semiconductor memory device having internal data read circuit excellent in noise immunity
10/08/2002US6462998 Programmable and electrically configurable latch timing circuit
10/08/2002US6462997 Circuit for resetting a pair of data buses of a semiconductor memory device
10/08/2002US6462996 Semiconductor integrated circuit device having internal synchronizing circuit responsive to test mode signal
10/08/2002US6462995 Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device
10/08/2002US6462993 Semiconductor integrated circuit
10/08/2002US6462992 Flash EEprom system
10/08/2002US6462988 Highly compact EPROM and flash EEPROM devices
10/08/2002US6462986 Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
10/08/2002US6462984 Biasing scheme of floating unselected wordlines and bitlines of a diode-based memory array
10/08/2002US6462983 Integrated semiconductor-magnetic random access memory system
10/08/2002US6462982 Magnetic random access memory having voltage control circuitry for maintaining sense lines at constant low voltages
10/08/2002US6462981 Magnetic random access memory
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