Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
12/2002
12/19/2002US20020192892 Method and circuit for generating reference voltages for reading a multilevel memory cell
12/19/2002US20020192887 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device
12/19/2002US20020191480 Clock synchronous semiconductor memory device
12/19/2002US20020191479 Semiconductor memory device operable for both of CAS latencies of one and more than one
12/19/2002US20020191477 A write circuit of a memory deivce
12/19/2002US20020191476 Semiconductor integrated circuit device and data writing method therefor
12/19/2002US20020191473 Semiconductor memory device and method of selecting word line thereof
12/19/2002US20020191472 Semiconductor memory device operating with low power consumption
12/19/2002US20020191470 Architecture, method(s) and circuitry for low power memories
12/19/2002US20020191468 Fuse circuit using anti-fuse and method for searching for failed address in semiconductor memory
12/19/2002US20020191467 Semiconductor memory device
12/19/2002US20020191466 System and method for performing partial array self-refresh operation in a semiconductor memory device
12/19/2002US20020191461 Reduced area sense amplifier isolation layout in a dynamic RAM architecture
12/19/2002US20020191459 Non-volatile memory device
12/19/2002US20020191451 Magnetoresistance effect device
12/19/2002US20020191448 Timing circuit and method for a compilable dram
12/19/2002US20020191447 Semiconductor integrated circuit
12/19/2002US20020191446 Semiconductor memory device having self-timing circuit
12/19/2002US20020191444 Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude
12/19/2002US20020191437 Magnetic memory device
12/19/2002US20020191436 Semiconductor memory device
12/19/2002US20020191435 Method for non-destructive readout and apparatus for use with the method
12/19/2002US20020190993 Image processing apparatus
12/19/2002US20020190992 Data processing system and image processing system
12/19/2002US20020190713 Magnetic device
12/19/2002US20020190304 Nonvolatile ferroelectric memory device
12/19/2002US20020190296 Nonvolatile memory and method for driving nonvolatile memory
12/19/2002US20020190291 Semiconductor memory device utilizing tunnel magneto resistive effects and method for manufacturing the same
12/19/2002US20020190265 T-Ram cell having a buried vertical thyristor and a pseudo-TFT transfer gate and method for fabricating the same
12/19/2002DE10220328A1 Schaltung zur Taktsignalerzeugung, zugehörige integrierte Schaltkreisbauelemente und Auffrischtaktsteuerverfahren Circuit for clock signal generation, associated integrated circuit devices and Auffrischtaktsteuerverfahren
12/19/2002DE10219165A1 Halbleiter-Speichereinrichtung A semiconductor memory device
12/19/2002DE10128964A1 Digital memory cells device, uses bias layer system with ferromagnetic layer
12/19/2002DE10127336A1 Semiconductor storage cell for DRAM, comprises storage capacitor which incorporates super ion conductor layer located between the capacitor electrodes
12/19/2002DE10121131C1 Datenspeicher Data storage
12/19/2002CA2447650A1 Sense amplifier with improved latching
12/18/2002EP1267356A2 ROM memory with multibit memory points
12/18/2002EP1267355A1 One-shot signal generating circuit
12/18/2002EP1267354A2 Semiconductor memory device, method for controlling same, and electronic information apparatus
12/18/2002EP1267353A2 Semiconductor integrated circuit device and data writing method therefor
12/18/2002EP1267272A2 A specialized memory device
12/18/2002EP1266381A1 Method and apparatus for an easy identification of a state of a dram generator controller
12/18/2002EP1266379A2 Method and apparatus for an improved reset and power-on arrangement for a dram generator controller
12/18/2002EP1163677B1 Integrated memory with memory cells and reference cells and corresponding operating method
12/18/2002EP1119860B1 Magnetoresistive memory having improved interference immunity
12/18/2002EP1112575B1 Magnetoresistive element and use of same as storage element in a storage system
12/18/2002EP1105890B1 Magnetoresistive element and the use thereof as storage element in a storage cell array
12/18/2002EP0956561B1 Differential flash memory cell and method
12/18/2002EP0880782B1 Multiple writes per a single erase for a nonvolatile memory
12/18/2002EP0853806B1 Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
12/18/2002EP0838057B1 Memory controller which executes write commands out of order
12/18/2002CN1386283A Integrated circuit containing SRAM memory and method of testing same
12/18/2002CN1385905A Magnetic RAM of transistor with vertical structure and making method thereof
12/18/2002CN1385896A Semiconductor memory with same property storage unit and making method thereof
12/18/2002CN1385860A Film magnet memory with magnetic tunnel junction
12/18/2002CN1385859A Electric resistance cross-point memory utilizing checking amplifier demarcating method on chip
12/18/2002CN1385858A Method for sensing non-volatility ferroelectric internal memory
12/18/2002CN1096683C Semiconductor storage device with data output path for quick access
12/18/2002CN1096682C Highly integrated storage unit and making method
12/18/2002CN1096680C 半导体存储装置 The semiconductor memory device
12/18/2002CN1096679C 动态存储器 Dynamic Memory
12/17/2002US6496897 Semiconductor memory device which receives write masking information
12/17/2002US6496445 Semiconductor memory device having altered clock frequency for address and/or command signals, and memory module and system having the same
12/17/2002US6496442 Dynamic random access memory device and semiconductor integrated circuit device
12/17/2002US6496441 Semiconductor memory device with improved data propagation characteristics of a data bus
12/17/2002US6496438 Semiconductor device and method for generating internal power supply voltage
12/17/2002US6496437 Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory
12/17/2002US6496436 Reference voltage generator for MRAM and method
12/17/2002US6496435 Sense amplifier control circuit of semiconductor memory device
12/17/2002US6496433 Semiconductor device and semiconductor device testing method
12/17/2002US6496430 Semiconductor memory circuit having selective redundant memory cells
12/17/2002US6496422 Memory structure utilizing four transistor load less memory cells and a bias generator
12/17/2002US6496421 Distributed cell plate and/or digit equilibrate voltage generator
12/17/2002US6496418 Semiconductor integrated circuit and data processing system
12/17/2002US6496415 Non-volatile memory device having high speed page mode operation
12/17/2002US6496412 Nonvolatile semiconductor memory device for storing multivalued data
12/17/2002US6496411 Non-volatile multi-level semiconductor flash memory device and method of driving same
12/17/2002US6496410 Concurrent program reconnaissance with piggyback pulses for multi-level cell flash memory designs
12/17/2002US6496409 Variable capacity semiconductor memory device
12/17/2002US6496408 Selective device coupling
12/17/2002US6496407 Ferroelectric memory
12/17/2002US6496403 Semiconductor memory device
12/17/2002US6496402 Noise suppression for open bit line DRAM architectures
12/17/2002US6496051 Output sense amplifier for a multibit memory cell
12/17/2002US6496043 Method and apparatus for measuring the phase of captured read data
12/17/2002US6496032 Method and structure for efficiently placing and interconnecting circuit blocks in an integrated circuit
12/17/2002US6495994 Regulator circuit for independent adjustment of pumps in multiple modes of operation
12/17/2002US6495873 Magnetoresistive element and use thereof as a memory element in a memory cell configuration
12/12/2002WO2002099906A1 Magnetoresistance element and magnetoresistance storage element and magnetic memory
12/12/2002WO2002099905A1 Tunnel magnetoresistance element
12/12/2002WO2002099813A2 Semiconductor storage location
12/12/2002WO2002099812A1 Semiconductor storage device
12/12/2002WO2002099811A1 Semiconductor storage device
12/12/2002WO2002099806A2 Novel method and structure for efficient data verification operation for non-volatile memories
12/12/2002WO2002099661A2 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
12/12/2002WO2002027729A3 Writable tracking cells
12/12/2002US20020188898 Tester built-in semiconductor integrated circuit device
12/12/2002US20020188893 Series connected TC unit type ferroelectric RAM and test method thereof
12/12/2002US20020188816 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
12/12/2002US20020186611 Semiconductor memory device having hierarchical word line structure
12/12/2002US20020186610 Integrated memory having a memory cell array with a plurality of segments and method for operating the integrated memory
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